Yin-Nien Chen

Design and Analysis of Robust Tunneling FET SRAM

With a steep subthreshold slope, tunneling FETs (TFETs) are promising candidates for ultralow-voltage operation compared with conventional MOSFETs. However, the delayed saturation characteristic and the broad soft transition region result in a large crossover region/current in an inverter, thus degrading the hold/read static noise margin (H/RSNM) of TFET SRAM cells. The write-ability and write static noise margin (WSNM) of TFET SRAM cells are constrained by the unidirectional conduction characteristics and large crossover contention of the write access transistor and the holding transistor. In this paper, we present a detailed analysis of TFET circuit switching/output characteristics/performance and the underlying physics. The stability/performance of several TFET SRAM cells are then analyzed/compared using atomistic technology computer-aided design mixed-mode simulations. Finally, a robust 7T driverless (DL) TFET SRAM cell is proposed. The proposed 7T DL TFET SRAM cell, with better output characteristics in single-gate mode, and decoupled read current path from cell storage node and push-pull write action with asymmetrical raised-cell-virtual-ground write-assist, provides a significant improvement in hold, read, and write stability and performance.

Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits

In this work, we propose a mixed TFET-MOSFET 8T SRAM cell comprising MOSFET cross-coupled inverters, dedicated TFET read stack and TFET write access transistors for ultra-low voltage operation. Exploiting both the merits of TFET and MOSFET devices, the proposed SRAM cell provides significant improvement in SRAM stability, Vmin and performance. The stability and performance of the proposed cell are evaluated and compared with the conventional MOSFET 8T cell and pure TFET 8T cell using mixed-mode TCAD simulations based on published design rules for 22 nm technology node. Besides, the impacts of the device design of the proposed SRAM cell on the stability are also investigated. Various write-assist techniques to enhance the write-ability across VDD= 0.2 to 0.7 V for these SRAM cells are comparatively assessed. The results indicate that the proposed mixed TFET-MOSFET cell topology is viable for ultra-low voltage operation while MOSFET cell provides better stability and performance for high voltage operation.

Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications

This paper investigates the impact of intrinsic random variability on the robustness of sense amplifier (SA) for fin-shaped field-effect transistor (FinFET) subthreshold static random access memory (SRAM) applications. We employ a model-assisted statistical approach to consider both fin line edge roughness (fin LER) and work function variation, which are regarded as the major variation sources in an advanced FinFET device. Our results indicate that fin LER dominates the overall variability of subthreshold SA robustness and sensing margin. In addition, it is observed that the offset voltage (VOS) of current latch SA calculated solely from threshold voltage (VT) mismatch underestimates the actual variation and is shown to be optimistic. For large-signal single-ended inverter sensing, we find that sense “0” hinders the allowable sensing margin and needs to be carefully designed. Compared with bulk CMOS, the superior electrostatic integrity and variability of FinFET enhance the feasibility of differential sensing in subthreshold SRAM applications.

Impacts of single trap induced random telegraph noise on finfet devices and SRAM cell stability

In this work, we investigate, for the first time, the impacts of single trap induced Random Telegraph Noise (RTN) on the drain current of FinFET devices and the stability of FinFET 6T SRAM cell. For FinFET operating in tied-gate mode, we show that the charged trap located near the bottom of the sidewall channel, at the middle of the channel between source/drain results in most significant impact (worst position). In independent-gate mode, degraded RTN is observed and depends on the relative location of the trap and current conduction path. In addition, our results indicate that the correlation between RTN and fin Line Edge Roughness (fin LER) and Work Function Variation (WFV) is not obvious as compared with the BULK counterpart. For 6T SRAM operating in subthreshold region, single charged trap for each individual cell transistor, placed at the worst position, forms 64 possible combinations and the resulting extreme values of cell stability during READ and WRITE operations are examined for various Vdd. Because of the reduced carriers with decreasing supply voltage, the relative importance of RTN on cell stability increases and hinders the cell stability of subthreshold 6T SRAM cell in the vicinity of distribution tail.

Stability and Performance Optimization of Heterochannel Monolithic 3-D SRAM Cells Considering Interlayer Coupling

This paper extensively evaluates the stability and performance of heterochannel 6T/8T SRAM cells integrated in monolithic 3-D scheme with interlayer coupling. Various bitcell layouts with different gate alignments of transistors from distinct layers are investigated. This paper indicates that stacking the NFET tier over the PFET tier results in larger design margins for cell robustness and performance. Furthermore, the partition of 3-D layout design among distinct layers shows profound impacts on the stability, standby leakage, and performance of monolithic 3-D SRAM cells. Compared with the Si-based cells, the use of heterochannel devices increases the improvements of monolithic 3-D design over the 2-D counterparts and emerges as a suitable candidate for future monolithic 3-D IC applications.

Investigation of single-trap-induced random telegraph noise for tunnel FET based devices, 8T SRAM cell, and sense amplifiers

This paper analyzes the impacts of Random Telegraph Noise (RTN) caused by a single acceptor-type trap on Tunnel FET (TFET) based devices, 8T SRAM cell and sense amplifiers. 3D atomistic TCAD simulations accounting for the impact of localized/negatively-charged trap are utilized to assess the dependence of RTN amplitude (ΔID/ID) on trap location and device geometry. Our results indicate that significant RTN impact occurs for trap located near the tunneling junction. The device design strategies (thinner EOT, Wfin and longer Leff) to improve TFET device characteristics are found to increase the susceptibility to RTN. Furthermore, TFET-based standard 8T SRAM cell and several commonly used sense amplifiers including Current Latch Sense Amplifier (CLSA), Voltage Latch Sense Amplifier (VLSA), and single-ended large-signal inverter sense amplifier are examined using atomistic 3D TCAD mixed-mode simulations. The presence of RTN is shown to cause extra ~16% variations in cell stability (at Vdd = 0.3V) and additional ~80mV variation in offset voltage for sense amplifiers at Vdd = 0.5V.

A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance

With steep sub-threshold slope, tunneling FETs (TFETs) are promising candidates for ultra-low voltage operation, achieving low leakage current and superior performance compared with the conventional MOSFETs. However, the broad soft transition region in the Id-Vgs characteristics, where Id increases slowly to reach saturation following the steep slope region, results in large crossover region/current in an inverter, thus degrading the Hold/Read Static Noise Margin (H/RSNM) of TFET SRAMs. The Write-ability and Write Static Noise Margin (WSNM) of TFET SRAMs are constrained by the uni-directional conduction characteristics caused by the asymmetric source-drain structure and large cross-over contention of the Write access transistor and the holding transistor. In this paper, we present a detailed analysis of TFET circuit switching characteristics/performance and compare the stability/performance of several TFET SRAM cells using atomistic TCAD mixed-mode simulations. A robust 7T Driver-Less (DL) TFET SRAM cell is proposed. The proposed 7T DL TFET SRAM cell, with decoupled Read current path from cell storage node and push-pull Write action with asymmetrical raised-cell-virtual-ground Write-assist, provides significant improvement in Read/Write stability and performance.

Investigation of Backgate-Biasing Effect for Ultrathin-Body III-V Heterojunction Tunnel FET

This paper investigates the impact of backgate biasing (V_BS) on the drain current (I_D) of ultrathin-body III-V heterojunction tunnel FET (HTFET). Compared with homojunction TFET and III-V/Ge MOSFET, this paper indicates that HTFET exhibits significantly higher I_OFF (I_D at VGS = 0 V and V_DS = 0.5 V) modulation efficiency and the influence of V_BS rapidly decreases with increasing V_GS. In addition, it is observed that the change of source available states with V_BS determines the I_D modulation efficiency of p-type HTFET (pHTFET). Depending on the source doping concentration and operating VGS, the I_D of HTFET under forward V_BS can be anomalously smaller than that at V_BS = 0 V. Furthermore, the impacts of source/drain doping concentrations and junction properties are discussed and shown to be critical in determining the I_D modulation efficiency of HTFET. We find that, under controlled ambipolar current, reverse backgate biasing can be utilized to suppress the I_OFF of HTFET, and the modulation efficiency increases with decreasing source doping concentration. Our study may provide insights for device/circuit designs with advanced TFET technologies.

Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell

In this work, we propose a mixed TFET-MOSFET 8T SRAM cell comprising MOSFET cross-coupled inverters, dedicated TFET read stack and TFET write access transistors. Exploiting both the merits of TFET and MOSFET devices, the proposed SRAM cell provides significant improvement in SRAM stability, Vmin and performance. The proposed cell is evaluated and compared with the conventional MOSFET 8T cell and pure TFET 8T cell using mixed-mode TCAD simulations. The results indicate that the proposed mixed TFET-MOSFET cell topology is viable for ultra-low voltage operation.

Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits

In this paper, we comprehensively review the impacts of single-trap-induced random telegraph noise (RTN) on FinFET, Ge/Si Nanowire FET and Tunnel FET (TFET). The resulting influences on the thermionic-based current conduction such as FinFET, Si-NW FET and Ge-NW FET (at low drain bias) as well as interband tunneling dominated current conduction such as TFET and high-drain-biased Ge-NW FET are extensively addressed in device and circuit level. The location of the trap is shown to have profound impacts and the impacts vary with bias conditions and trap types. The worst-case analysis of the stability/performance and leakage/delay for all possible trapping/detrapping RTN combinations are investigated for FinFET, Si-/Ge-NW FETs and TFET based 6T/8T SRAM cells and logic circuits.