Ching-Te Chuang

Turning silicon on its edge [double gate CMOS/FinFET technology]

Double-gate devices will enable the continuation of CMOS scaling after conventional scaling has stalled. DGCMOS/FinFET technology offers a tactical solution to the gate dielectric barrier and a strategic path for silicon scaling to the point where only atomic fluctuations halt further progress. The conventional nature of the processes required to fabricate these structures has enabled rapid experimental progress in just a few years. Fully integrated CMOS circuits have been demonstrated in a 180 nm foundry-compatible process, and methods for mapping conventional, planar CMOS product designs to FinFET have been developed. For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.

SOI for digital CMOS VLSI: design considerations and advances

This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAMs), dynamic random access memories (DRAMs), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting from the unique SOI device structure. The impact of floating-body in partially depleted devices on the circuit operation, stability, and functionality are addressed. The use of smart-body contact to improve the power and delay performance is discussed, as are global design issues.

The impact of gate-oxide breakdown on SRAM stability

We have investigated the effects of oxide soft breakdown (SBD) on the stability of CMOS 6T SRAM cells. Gate-to-diffusion leakage currents of 20-50 /spl mu/A at the n-FET source can result in a 50% reduction of noise margin. Breakdown at other locations in the cell may be less deleterious depending on n-FET width. This approach gives targets for tolerable values of leakage caused by gate-oxide breakdown.

Design and CAD Challenges in sub-90nm CMOS Technologies

This paper discusses design challenges of scaled CMOS circuits insub-90nm technologies for high-performance digital applications.To continue scaling of the CMOS devices deep into sub-90nm tech-nologies,fully depleted SOI, strained-Si on SiGe, FinFETs withdouble gate, and even further, three-dimensional circuits will be uti-lizedto design high-performance circuits. We will discuss uniquedesign aspects and issues resulting from this scaling such as gate-to-body tunneling, self-heating, reliability issues, and process vari-ations.As the scaling approaches various physical limits, new SOIdesign issues such as Vt modulation due to leakage, low-voltageimpact ionization, and higher V{t,lin} to maintain adequate V{t,sat},continue to surface.With an eye towards the future, design andCAD issues related to sub-65nm device structures such as doublegate FinFET will be discussed.

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-interleaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with VDD down to 0.35 V ( 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 μW power. Data is held down to 0.275 V with 2.29 μW Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for VDD around/above 1.0 V.

Random Dopant Fluctuation in Limited-Width FinFET Technologies

In this brief, the random-dopant-fluctuation (RDF) effects in FinFET devices are investigated via physical analyses and numerical simulations. Our results show that extremely scaled devices, particularly FinFETs with narrow device width (fin height) in each individual fin, are susceptible to RDF effects. Even in an ideally ldquoundopedrdquo silicon channel, the existence of unintended impurity dopants of acceptors and donors will still have a significant impact on device characteristics. The implication from RDF for design is also discussed.

High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices

Novel high-density logic-circuit techniques employing independent-gate controlled double-gate (DG) devices are proposed. The scheme utilizes the threshold-voltage (VT) difference between double-gated and single-gated modes in a high-VT DG device to reduce the number of transistors required to implement the stack logic. In a series-connected stack portion of the logic gate, the number of transistors is halved, thus substantially improving the area/capacitance and the circuit performance. The scheme can be easily implemented by a DG technology with either a metal gate or a polysilicon gate. Six-way logic can be implemented with the proposed scheme using only six transistors. The viability and performance advantage of the scheme are validated via extensive mixed-mode physics-based numerical simulations

Floating-body effects in partially depleted SOI CMOS circuits

This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on circuit topologies where the parasitic bipolar effect resulting from the floating body affects the circuit operation and stability. Commonly used circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits and Manchester carry chains, are examined. Pass-transistor-based designs including latch, multiplexer, and pseudo two-phase dynamic logic are then discussed. It is shown that under certain circuit topologies and switching patterns, the parasitic bipolar effect causes extra power consumption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for.

Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability

Negative and Positive Bias Temperature Instabilities (NBTI (in PFET) and PBTI (in NFET)) weaken MOSFETs with time. The impact of such device degradation can be severe in Static Random Access Memories (SRAMs) wherein stability is governed by relative strengths of FETs. Degradation in stability with time under ‘worst case condition’ gets more important because of reduced guard-banding due to process induced instability. In this work, circuit insights into worst-case conditions and effect of NBTI and PBTI, individually and in combination, on the stability of an SRAM cell are presented. It is shown that measurable quantities such as static noise-margin are not sufficient to completely understand the combined effect of NBTI and PBTI. Monte-Carlo simulations are performed in a 45 nm PDSOI technology to estimate the increase in cell failure probability with time. In worst case, NBTI and PBTI both degrade read stability (significantly) and writability (marginally). Further, we analyze the choice of optimal power supply considering the trade-off between short-term stability (due to process variations) and long-term stability (due to NBTI/PBTI) to achieve six-sigma confidence in SRAM cell robustness.

Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure

An on-chip digital characterization method for local random variation in a process is presented. The method uses a sense-amplifier-based test circuit that uses digital voltage measurement instead of the analog current measurements of conventional techniques. The proposed circuit helps design fast on-chip built-in-self-test schemes for measuring random variation. A testchip is designed in 0.13mum CMOS and measured to show the effectiveness of the proposed circuit in extracting local random variation.