Yinan Shen

Protocol conformance testing using unique input/output sequences

Conformance testing for verification and validation of protocols for communication/distributed computer systems are the features of this book. The reader is introduced to this topic using the finite state machine (FSM) model together with a comprehensive review of past and current work. A detailed treatment of graph approaches for vector generation and fault coverage evaluation is presented using examples with real protocols. Qualitative and quantitative measures are introduced to quantify and compare these approaches, inclusive of the length of the generated test sequence and fault detection capabilities. Different techniques such as the rural Chinese postman tour and compaction by test overlapping, are fully analyzed for achieving the desired figures of merit. Novel analytical frameworks such as the fault model and the test sequence generation, are proposed to facilitate a better understanding of the conformance testing process for the practicing engineer as well as an academia audience.

Design for testability techniques for CMOS combinational gates

The design of easily testable CMOS combinational circuits is discussed. Two CMOS structured design techniques are presented. The novelty of this approach is the complete fault detection of single- and multiple-line stuck-at, transistor stuck-open, and stuck-on faults for combinational circuits. The test algorithm requires only minimal modifications to detect a large number of bridging faults. These techniques are both based on the addition of two transistors, a P-FET and an N-FET, which are placed in series between the P and N sections. In the first case (dynamic fully CMOS, DFCMOS), the transistors are controlled by a single input; in the other case (testable fully CMOS, TFCMOS), there is one input for each additional transistor. The test procedure is presented, and it is shown that multiple fault detection can be easily achieved. >

Guidelines for testing WSI sequential arrays

New results on generating a functional test procedure for linear arrays composed of sequential cells are presented. The sequential cell is modeled as a finite state machine and the testing process is characterized by the definition of a test sequence for each transition of the finite state machine, by means of the unique input/output sequence technique. The two sets of conditions that are defined (for controllability and observability) allow testing of a one-dimensional sequential array in linear time. The methodology presented has been applied to a number of different examples of sequential linear arrays (convolvers, complex multipliers, and FFT arrays), and fault coverage obtained by considering the single stuck-at fault model was evaluated.<<ETX>>

Detection of multiple faults in CMOS circuits using a behavioral approach

Presents an approach for the detection of multiple stuck-open (SOP) and stuck-on (SON) faults in CMOS combinational logic circuits. It is proved that multiple SON and SOP faults do not mask each other. This is achieved using a behavioral analysis in which the maskable fault patterns are proved to be impossible. New testing approaches are proposed. Testing is implemented using a combination of two-pattern test sequences as well as universal test sets, as proposed in previous papers by different authors.<<ETX>>

Fault-tolerant tree architecture with improved reconfiguration capabilities

A new approach is presented for the reconfiguration of VLSI tree architectures. It is based on a process of logical displacement for accomplishing reconfiguration with the global availability of redundant cells (or spares). A new and simple switch structure is proposed which allows flexibity in routing and spare allocation to accomplish a double displacement in the reconfiguration process. The proposed switch structure also permits a fully global execution of the reconfiguration process as the reconfigured tree spans the whole structure, not only a subtree as in previous approaches. Overhead issues with respect to the number of spares and redundant links are addressed. The conditions for reconfigurability are fully analysed; it is proved that the ability to reconfigure in the presence of a double displacement results in an improvement in reconfigurability. Faults in basic cells, links and switching circuits are considered. A lower bound on the improvement of reconfigurability is established. Simulation re...

Concurrent built-in self-test with reduced fault latency

Presents various new approaches for concurrent built-in self-test (CBIST). These new approaches have a low latency in fault detection. Two approaches are proposed. The first approach is applicable to combinational logic circuits which can be designed using iterative logic arrays (ILAs). Two methods namely the HIT-COMPRESS and HIT-IDENTICAL, are discussed. These methods employ different hardware structures to accomplish on-line detection. The second approach is applicable to sequential circuits. Two implementations are presented. The first implementation is based on a ring counter, while the second implementation utilizes a parity tree. The principles of operation of these approaches have been fully analyzed and it is proved that fault latency is considerably less than in previous approaches. Hardware overhead issues are also analyzed.<<ETX>>

Fault detection in a testable PLA with low overhead for production testing

A testable structure is presented for programmable logic arrays (PLAs) which is amenable to production testing. A low overhead structure is proposed to keep the kill area at the lowest value. This is achieved by using a single additional input line to the original PLA. Fault detection is based on a specific set of conditions which must be satisfied in the characteristic matrix and structure of the minimized PLA. The characteristics of the vectors in the test set are discussed. A two-phase test is used to supplement the basic test vector if the specified constraint in the minimized PLA structure is not met. Hardware overhead is lower than any other method found in the technical literature.<<ETX>>