Jon C. Muzio

Antisymmetries in the realization of Boolean functions

New symmetries of degree two are introduced, along with spectral techniques for identifying these symmetries. Some applications of these symmetries are discussed, in particular their application to the construction of binary decision diagrams and the implementation of Boolean functions.

Built-in self-testable data path synthesis

In this paper, we describe a high-level data path allocation algorithm to facilitate built-in self test. It generates self-testable data path design while maximizing the sharing of modules and test registers. The sharing of modules and test registers enables only a small number of registers is modified for BIST, thereby decreasing the hardware area which is one of the major overheads for BIST technique. In our approach, both module allocation and register allocation are performed incrementally. In each iteration, module allocation is guided by a testability balance technique while register allocation aims at increasing the sharing degrees of registers. With a variety of benchmarks, we demonstrate the advantage of our approach compared with other conventional approaches.

Properties of autocorrelation coefficients

The use of spectral techniques in logic synthesis is well researched and well known. However, there is very little work surrounding the use of other transforms such as the autocorrelation transform. This paper introduces a variety of properties inherent to the coefficients produced by the autocorrelation transform, and discusses potential applications.

Introducing redundant transformations for high level built-in self-testable synthesis

In our previous work (Proc. ICECS-01, vol. 1, pp. 549-552, 2001; Proc. SBCCI-01, pp. 115-121, 2001), we describe an integrated high-level synthesis algorithm for operation scheduling and data path allocation to facilitate built-in self-test designs. In this paper, we make use of two types of redundant transformations for the integrated synthesis algorithm, which add redundancy which improves test resources to be shared in the data path and operation scheduling. With a variety of benchmarks, we demonstrate the advantage of the approach by introducing redundant transformations compared with our previous and other conventional approaches.

Introducing redundant transformations for built-in self-testable data path allocation

In our previous work, we described a high-level data path allocation algorithm to facilitate built-in self-test designs. In this paper, we make use of two types of redundant transformations, which add redundancy that improves test resources to be shared in the data path, to improve our previous data path allocation algorithm. The algorithm generates self-testable data path design while maximizing the sharing of modules and test registers. The sharing of modules and test registers enables only a small number of registers to be modified for BIST, thereby decreasing the hardware area which is one of the major overheads for the BIST technique. With a variety of benchmarks, we demonstrate the advantage of our approach compared with our previous and other conventional approaches.

A high-level data path allocation algorithm based on BIST testability metrics

In this paper, we describe a BIST testability metric-based high-level data path allocation algorithm to facilitate Built-In Self-Test designs. We will describe register transfer level data path testability metrics to evaluate various BIST configurations and make improvement decision during the data path allocation. With a variety of benchmarks, we demonstrate the advantage of our approach compared with other conventional approaches.

A register-transfer level BIST partitioning approach for ASIC designs

Various approaches have been proposed to enhance the testability of VLSI by incorporating extra testability features. Recent advances in VLSI technology are motivating changes in the traditional methods of design and test, leading to the integration of design and test activities. Testability, defined as the facility to generate and apply test, is added as a new constraint to the synthesis process and design modifications are proposed to improve testability. One popular design for testability methodology is built-in self-test (BIST) techniques, where pseudo-random pattern generators (RTPG) generate and supply test patterns and multi-input signature registers (MISR) compress test responses. These techniques involve modification of the hardware on the chip so that the chip has the capability to test itself. The goal of this paper is to develop a new improvement method with BIST technique at register transfer level (RTL).

High-level data path synthesis for built-in self-test designs

The sharing of modules and test registers ensures only a small number of registers is modified for BIST, thereby decreasing the hardware area which is one of the major overhead for BIST technique. In this approach, both module allocation and register allocation are performed incrementally. In each iteration, module allocation is guided by a testability balance technique while register allocation aims at increasing the sharing degrees of registers. In this paper, we would like present two improvement techniques, namely the resource optimization approach before the synthesis algorithm and high-level automatic BIST configuration after the synthesis algorithm. With a variety of benchmarks, we demonstrate the advantage of the improvement approaches compared with previous results.

Using Multimedia in a Digital Design Lab

We introduce a multimedia-based Virtual lab, developed with Macromedia Director, to enable students in Digital Logic Design courses to practice, exercise, learn in a simulated environment, easily integrated with more traditional physical lab boards.