Yinan Sun

An energy-efficient heterogeneous dual-core processor for Internet of Things

With the fast development of Internet of Things (IoTs) in recent years, many IoT applications, such as structure health monitoring, surveillance camera and etc, require both extensive computation for burst-mode signal processing as well as ultra low power continuous operations. However, most of conventional IoT processors focus on ultra low power consumption and cannot satisfy those demands. This paper proposes a novel energy-efficient heterogenous dual-core processor, which includes both an ultra low power near-threshold CoreL and a fast CoreH to meet those emerging requirements. Furthermore, an optimal framework is proposed to realize energy efficient task mapping and scheduling. The processor is fabricated and its energy consumption in low power mode is as low as 7.7pJ/cycle and outperforms related work. Detailed analysis under several real applications shows that up to 2.62× energy efficiency improvements can be achieved without deadline miss compared with the high-performance-only signle core architecture.

Design methodology of variable latency adders with multistage function speculation

Increasing circuit delay range due to process variations, temperature and voltage fluctuations and input characterization makes the traditional worst-case fault-avoidance design methodology no longer sustainable. As an alternative, the average-case fault-detection design methodology is generating interest. Among existing solutions, function speculation design with error recovery mechanisms is quite promising due to its high performance and low area overhead. Previous work had focused on two-stage function speculation and thus lacked a systematic way to address the challenge of the multistage function speculation approach. For the first time, this paper proposes a multistage function speculation structure and applies it in a novel adder. We deduced the analytical performance and area models for the design and validated them in our experiments. Based on those models, a general methodology is presented to guide design optimization. Both analytical proofs and experimental results show that the proposed adders delay and area has a logarithmic and linear relationship with its bit number,respectively. Compared with the DesignWare IP, the proposed adder provides the same performance with 6–16% area reductions under different bit number configurations.

From device to system: cross-layer design exploration of racetrack memory

Recently, Racetrack Memory (RM) has attracted more and more attention of memory researchers because it has advantages of ultra-high storage density, fast access speed, and non-volatility. Prior research has demonstrated that RM has potential to replace SRAM for large capacity on-chip memory design. At the same time, it also addressed that the design space exploration of RM could be more complicated compared to traditional on-chip memory technologies for several reasons. First, a single RM cell introduces more device level design parameters. Second, considering these device-level design factors, the layout exploration of a RM array demonstrates trade-off among area, performance, and power consumption of RM circuit level design. Third, in the architecture level, the unique “shift” operation results in an extra dimension for design exploration. In this paper, we will review all these design issues in different layers and try to reveal the relationship among them. The experimental results demonstrate that cross-layer design exploration is necessary for racetrack memory. In addition, a system level case study of using RM in a sensor node is presented to demonstrate its advantages over SRAM or STT-RAM.

An energy efficient fully integrated OOK transceiver SoC for wireless body area networks

This work presents a low-power high-speed system-on-chip (SoC) for wireless body area networks (WBANs). The SoC is fully integrated with a 10 Mb/s on-off keying (OOK) RF transceiver, digital processing units, an 8051 micro-controlled unit (MCU), a successive approximation (SAR) ADC, and etc. The receiver adopts envelop detector (ED) based structure to improve the energy efficiency. Conventional ED based structure has a poor sensitivity when reaching a bit rate of Mb/s level. To resolve the problem, we design a receiving (Rx) front-end with 77 dB gain at 10 Mb/s data rate, and propose a novel supply isolation scheme to avoid the instability induced by such a high gain. The transmitter is based on a 2 GHz digitally controlled oscillator (DCO), which uses bond wires as inductors to further reduce the power at transmitting (Tx) mode. The digital baseband is designed by a near-threshold design (NTD) method for low power consumption. The chip is implemented with 0.13 μm CMOS technology, measured results show that the receiver consumes 0.214 nJ/bit at -65 dBm sensitivity, and the Tx energy efficiency is 0.285 nJ/bit at an output power of -5.4 dBm. In addition, the digital baseband consumes 34.8 pJ/bit with its supply voltage lowered to 0.55 V, indicating its energy per bit is reduced to nearly 1/4 of the super-threshold operation.

Ferroelectric Nonvolatile Processor Design, Optimization, and Application

Nonvolatile processor (NVP) is one of the most promising techniques to realize energy-efficient computing systems with zero standby power, instant-on features, high resilience to power failures, and fine-grained power management. As flip-flops as well as static random access memories (SRAM) should be replaced by nonvolatile memory in an NVP, it puts rigid requirements on the nonvolatile memories, such as nearly unlimited operation cycles, ultra-short access time and easy integration to CMOS technology. Ferroelectric memory can meet those metrics with good energy efficiency, which is appropriate to realize an NVP. However, there are several major design problems, such as the unknown design flow of a ferroelectric NVP, the nontrivial area overheads as well as the absent of the real application systems. To overcome those challenges, we present the first fabricated NVP with zero standby power, \(7\,\upmu \text {s}\) sleep time and \(3\,\upmu \text {s}\) wake-up time, consisting of a flip-flop controller (FFC), a distributed memory architecture and a voltage detection system. Compared with an existing industry processor, it can achieve over 30–\(100\times \) speedup on the wake-up/sleep time and \(70\times \) energy savings on the data backup and recall operations. Meanwhile, the ferroelectric NVP exhibits comparative performance and power consumption in normal operations. To attack its area challenges, we design a parallel compare-and-compress architecture (PaCC) and an appropriate vector selecting method to reduce the number of nonvolatile registers by 70–80 % with less than 1 % overflow possibility, which leads to up to 30 % processor area savings. Another segment-based parallel compression (SPaC) architecture is proposed to trade off the chip area and the backup speed. It divides the system vector into several segments and compresses them in parallel. Compared with the PaCC solution, it can improve the backup speed by 83 % with 16 % area savings over the full replacement architecture. Finally, we demonstrate two kinds of battery-less sensor nodes based on the NVP for the first time. They aimed at the moving object detection and the body sensor applications. As both systems are powered by energy-harvesting systems, they eliminate the battery lifetime constraints and work reliably under frequency power failures.

Maximum Energy Efficiency Tracking Circuits for Converter-Less Energy Harvesting Sensor Nodes

Converter-less supply architecture is promising for energy harvesting sensor nodes, due to their high conversion efficiency, low cost, and easy integration. However, lack of a dc-dc converter precludes the electronic load operating under the voltage for optimal energy efficiency, since the output voltage of the energy harvester is set as the maximum power point tracking (MPPT) voltage. To mitigate efficiency loss of workload, we propose an architecture to achieve maximum energy efficiency tracking for the overall sensor node. A theoretical analysis is given for the architecture and an efficiency-driven frequency controller is fabricated to validate the design methodology. Measured results demonstrate that up to 162% performance gain of the overall sensor node is achieved compared with the existing systems with MPPT.

Power System Design and Task Scheduling for Photovoltaic Energy Harvesting Based Nonvolatile Sensor Nodes

This chapter proposes a novel high-efficiency PV power system for nonvolatile sensor nodes. It demonstrates that the storage-less and converter-less system achieves near 90 % energy efficiency by eliminating energy loss from power converters and storage devices. Furthermore, we propose a dual-channel power supply architecture to improve the quality of service when there are time mismatches between harvested energy and workload. A channel controller dynamically selects either direct channel or indirect one to maximize the energy efficiency under failure rate constraints. Both a simulation platform and a prototype are built to validate the architecture. Finally, we presented an intra-task scheduling algorithm for the storage-less and converter-less channel, which leverages neural network training based on solar profiles and task execution. Compared to the inter-task scheduling, it tracks solar variations more quickly and a much lower deadline missing rate is achieved.

Design methodology of multistage time-domain logic speculation circuits

As variable delays are observed in the integrated circuits under different data inputs, it is expected to enhance the performance of the circuit using the average-case design methodology. This paper presents a novel approach using the time-domain multistage speculation to realize a variable-latency circuit, in which speculation points with double-sampling and check-recovery units are inserted into the critical path to enhance the performance. Furthermore, a design framework is implemented to convert a original circuit into the new one automatically. Experimental results showed that a 1.79 – 4.42 speedup in a 64-bit ripple carry adder and up to 30.5% throughput enhancements in several ISCAS and MCNC benchmarks with reasonable area overheads.

Design of Ultra-Low-Power Electrocardiography Sensors

In this chapter, we present two key designs for ultra-low-power electrocardiography sensors, i.e., an event-driven analog-to-digital converter (ADC) and an on-off keying (OOK) transceiver. For the ADC, two QRS detection algorithms, pulse-triggered (PUT) and time-assisted PUT (t-PUT), are proposed based on the level-crossing events generated from the ADC. For the transceiver SoC, we propose a novel supply isolation scheme to avoid the instability induced by such a high receiver gain, use bond wires as inductors to reduce the transmitter power, and utilize near-threshold design (NTD) method for low power digital baseband. Fabricated in 0.13 \(\upmu \mathrm{m}\) CMOS technology, the ADC with QRS detector consumes only 220 nW measured under 300 mV power supply, making it the first nanoWatt compact analog-to-information (A2I) converter with embedded QRS detector. The transceiver SoC is fully integrated with a 10 Mb/s transceiver, digital processing units, an 8051 micro-controlled unit (MCU), a successive approximation (SAR) ADC, and etc. The receiver consumes 0.214 nJ/bit at − 65 dBm sensitivity, and the Tx energy efficiency is 0.285 nJ/bit at an output power of − 5. 4 dBm. In addition, the digital baseband consumes 34.8 pJ/bit with its supply voltage lowered to 0.55 V, indicating its energy per bit is reduced to nearly 1/4 of the super-threshold operation.

A Low Power Speed-configurable SoC Supporting Enhanced IEEE 802.15.4 Standard Digital Baseband Chip Design

This paper presented a configurable low power chip supporting enhanced 802.15.4 standard. Compared with previous works, we adopted a flexible architecture ranging from 125kbps to 500kbps under different requirements. A differential non-coherent demodulator is implemented to reduce the power consumption. The chip had been fabricated in SMIC 0.13um CMOS process, and measured results verified the design specification.