Ying-Cherng Lan

BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel

A Bidirectional channel Network-on-Chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication. The BiNoC allows each communication channel to be dynamically self-configured to transmit flits in either direction in order to better utilize on-chip hardware resources. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate at each on-chip router. In this paper, a novel on-chip router architecture supporting the sel-fconfiguring bidirectional channel mechanism is presented. It is shown that the associated hardware overhead is negligible. Cycle-accurate simulation runs on this BiNoC network under synthetic and real-world traffic patterns demonstrate consistent and significant performance advantage over conventional mesh grid NoC architecture equipped with hard-wired unidirectional channels.

A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel

A bidirectional channel network-on-chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication. In a BiNoC, each communication channel allows to be dynamically self-reconfigured to transmit flits in either direction. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate. Novel on-chip router architecture is developed to support dynamic self-reconfiguration of the bidirectional traffic flow. This area-efficient BiNoC router delivers better performance and requires smaller buffer size than that of a conventional network-on-chip (NoC). The flow direction at each channel is controlled by a channel direction control (CDC) algorithm. Implemented with a pair of finite state machines, this CDC algorithm is shown to be high performance, free of deadlock, and free of starvation. Extensive cycle-accurate simulations using synthetic and real-world traffic patterns have been conducted to evaluate the performance of the BiNoC. These results exhibit consistent and significant performance advantage over conventional NoC equipped with hard-wired unidirectional channels.

Networks on chips: structure and design methodologies

The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for on-chip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.

QoS aware BiNoC architecture

A quality-of-service (QoS) aware, bi-directional channel NoC (BiNoC) architecture is proposed to support guarantee-service (GS) traffic while reducing packet delivery latency. By incorporating dynamically self-reconfigured bidirectional communication channels between adjacent routers, BiNoC architecture promises more flexibility for various traffic flow patterns. A novel inter-router communication protocol is proposed that prioritizes bandwidth arbitration in favor of high priority GS traffic flows. Multiple virtual channels with prioritized routing policy are also implemented to facilitate data transmission with QoS considerations. Combining these architectural innovations, the QoS aware BiNoC promises reduced latency of packet delivery and more efficient channel resource utilizations. Cycle-accurate simulations demonstrate significant performance advantage over conventional unidirectional NoC architecture equipped with hard-wired unidirectional channels.

Fluidity concept for NoC: A congestion avoidance and relief routing scheme

In this paper, we utilize a novel fluidity concept to analyze and develop routing algorithms in network-on-chip for congestion avoidance and relief. We develop a new model to capture congestion information which improves the performance of routing algorithms. Comparisons of algorithms using our model consistently outperform the original algorithms themselves.

Performance-energy tradeoffs in reliable NoCs

Todays process technologies place emphasis on low power design in multi-core systems that require the complicate communication networks-on-chip (NoC) architecture to be reliable. Considering the many error control codes (ECCs) implemented in a hardware NoC router, the primary objective of this paper is accounting for the causes of energy consumed for fault tolerance and providing a way of comparison among different ECC methods. To make a proper choice, tradeoff between power and throughput of each ECC achieving the same reliability must be considered. Hence, some low-overhead ECC methods used in NoC have been implemented in hardware and their performance-energy tradeoff shown.

Reconfigurable Networks-on-Chip

This book provides a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip. It addresses a wide spectrum of on-chip communication problems, ranging from physical, network, to application layers. Specific topics that are explored in detail include packet routing, resource arbitration, error control/correction, application mapping, and communication scheduling. Additionally, a novel bi-directional communication channel NoC (BiNoC) architecture is described, with detailed explanation. Written for practicing engineers in need of practical knowledge about the design and implementation of networks-on-chip; Includes tutorial-like details to introduce readers to a diverse range of NoC designs, as well as in-depth analysis for designers with NoC experience to explore advanced issues; Describes a variety of on-chip communication architectures, including a novel bi-directional communication channel NoC.From the Foreword: Overall this book shows important advances over the state of the art that will affect future system design as well as R&D in tools and methods for NoC design. It represents an important reference point for both designers and electronic design automation researchers and developers. --Giovanni De Micheli

Flow Maximization for NoC Routing Algorithms

In this paper, we apply flow maximization and develop a minimal adaptive routing scheme towards lower average packet latencies in a network-on-chip. The minimal adaptive algorithm allows packets to be forwarded in multiple directions. Typical routing algorithms select the next hop path for each packet and then resolve conflicts between packets that have been selected to have the same next hop path. We propose a novel decision flow which combines routing direction and port arbitration while maximizing flow. Upon a 2-D mesh NoC, our implementation lowers average packet latencies across all packet injection rates of an NoC.

A novel flow fluidity meter for BiNoC bandwidth resource allocation

An enhanced on-chip network resource allocation method is developed for the Bi-directional Network-on-Chip (BiNoC) platform. Specifically, a novel flow Fluidity Meter (FM) is proposed to provide the real-time estimate of bandwidth utilization of the Virtual Channel (VC) buffer in a BiNoC router. The degree of fluidity of a packet transfer in each router is a reliable, yet low-cost method for measuring bandwidth utilization in the VC. We show that the overhead implementing this FM is very affordable. Finally, extensive simulation results verify that this proposed FM approach achieves superior performance compared to existing BiNoC resource allocation methods.

DyML: Dynamic Multi-Level flow control for Networks on Chip

A novel hybrid Dynamic Multi-Level (DyML) flow control scheme for Networks-on-Chip is proposed. DyML uses a buffer fluidity flow monitor for real-time monitoring the incoming traffic volume. Instead of buffering as many flits as a router can afford, DyML dynamically adjusts the proper number of buffering flits. Accordingly, DyML causes less in-transit packets in the network, thus improves packet latency and mitigates traffic congestion. Experiments indicated that DyML averagely improves the latency performance of a state-of-the-art routing algorithm (Odd-Even) by 25.43% in synthetic traffics and by 0.90% in real traffics.