Sao-Jie Chen

RTWPMS: A Real-Time Wireless Physiological Monitoring System

This paper demonstrates the design and implementation of a real-time wireless physiological monitoring system for nursing centers, whose function is to monitor online the physiological status of aged patients via wireless communication channel and wired local area network. The collected data, such as body temperature, blood pressure, and heart rate, can then be stored in the computer of a network management center to facilitate the medical staff in a nursing center to monitor in real time or analyze in batch mode the physiological changes of the patients under observation. Our proposed system is bidirectional, has low power consumption, is cost effective, is modular designed, has the capability of operating independently, and can be used to improve the service quality and reduce the workload of the staff in a nursing center

BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel

A Bidirectional channel Network-on-Chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication. The BiNoC allows each communication channel to be dynamically self-configured to transmit flits in either direction in order to better utilize on-chip hardware resources. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate at each on-chip router. In this paper, a novel on-chip router architecture supporting the sel-fconfiguring bidirectional channel mechanism is presented. It is shown that the associated hardware overhead is negligible. Cycle-accurate simulation runs on this BiNoC network under synthetic and real-world traffic patterns demonstrate consistent and significant performance advantage over conventional mesh grid NoC architecture equipped with hard-wired unidirectional channels.

A fault-tolerant NoC scheme using bidirectional channel

A novel Bidirectional Fault-Tolerant NoC (BFT-NoC) architecture capable of mitigating both static and dynamic channel failures is proposed. In a traditional NoC platform, a faulty data channel will force blocked packets to make costly detours, resulting in significant performance hits. In this work, novel fault-tolerance measures for a bidirectional NoC platform are proposed. The dynamically reconfigurable bidirectional channels of the BFT-NoC offer great flexibility to contain data-link permanent or transient faults while incurring negligible performance loss. Potential performance advantages in terms of failure rate reduction and reliability enhancement of the BFT-NoC architecture are carefully analyzed. Extensive experimental results clearly validate the fault-tolerance performance of BFT-NoC at both synthetic and real world network traffic patterns

A Fast Crosstalk- and Performance-Driven Multilevel Routing System

In this paper, we propose a novel framework for fast multilevelrouting considering crosstalk and performance optimization. To handlethe crosstalk minimization problem, we incorporate an intermediatestage of layer/track assignment into the multilevel routing framework.For performance-driven routing, we propose a novel minimum-radiusminimum-cost spanning-tree (MRMCST) heuristic for global routing.Compared with the state-of-the-art multilevel routing, the experimentalresults show that our approach achieved a 6.7X runtime speedup, reducedthe respective maximum and average crosstalk (coupling length)by about 30% and 24%, reduced the respective maximum and averagedelay by about 15% and 5%, and resulted in fewer failed nets.

An auto-I/Q calibrated CMOS transceiver for 802.11 g

The CMOS transceiver IC uses the superheterodyne architecture to implement a IEEE 802.11g RF front-end with auto I/Q calibration function. 1/spl deg/ quadrature mismatch and 0.1 dB gain mismatch can be achieved after the auto tuning in both the transmitter and receiver sides. Implemented in a 0.25 /spl mu/m CMOS process with 2.7 V supply, the transceiver achieves a 5.1 dB receive cascade NF and a 7 dBm transmit output P/sub 1dB/.

Crosstalk- and performance-driven multilevel full-chip routing

In this paper, we propose a novel framework for fast multilevel routing considering crosstalk and performance optimization. To handle the crosstalk minimization problem, we incorporate an intermediate stage of layer/track assignment into the multilevel routing framework. For performance-driven routing, we propose a novel minimum-radius minimum-cost spanning tree heuristic for global routing. Compared with the state-of-the-art multilevel routing with the routability mode, the experimental results show that our router achieved a 6.7X runtime speedup, reduced the respective maximum and average crosstalk (coupling length) by about 30% and 24%, reduced the respective maximum and average delay by about 15% and 5%. Compared with the timing-driven mode, the experimental results show that our router still achieved a 5.9X runtime speedup, reduced the respective maximum and average crosstalk by about 35% and 23%, reduced the respective maximum and average delay by about 7% and 10% in comparable routability, and resulted in fewer failed nets.

Multilevel routing with antenna avoidance

As technology advances into the nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasma-induced gate oxide degradation caused by charge accumulation on conductors. It directly influences manufacturability and yield of VLSI circuits, especially in deep-submicron technology using high density plasma. Furthermore, the continuous increase of the problem size of IC routing is also a great challenge to existing routing algorithms. In this paper, we propose a novel framework for multilevel full-chip routing with antenna avoidance using a built-in jumper insertion approach. Experimental results show that our approach reduced antenna-violated gates by about 98% and also achieved 100% routing completion for all circuits.

A novel low-power 64-point pipelined FFT/IFFT processor for OFDM applications

4G and other wireless systems are currently hot topics of research and development in the communication field. Broadband wireless systems based on orthogonal frequency division multiplexing (OFDM) often require an inverse fast Fourier transform (IFFT) to produce multiple subcarriers. In this paper, we present the efficient implementation of a pipeline FFT/IFFT processor for OFDM applications. Our design adopts a single-path delay feedback style as the proposed hardware architecture. To eliminate the read-only memories (ROMs) used to store the twiddle factors, the proposed architecture applies a reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT/IFFT processor, thus consuming lower power than the existing works. The design spends about 33.6K gates, and its power consumption is about 9.8mW at 20MHz.

Multilevel full-chip routing for the X-based architecture

As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been proposed for high-performance integrated circuits. The X-architecture presents a new way of orienting a chips microscopic interconnect wires with the pervasive use of diagonal routes. It can reduce the wire-length and via count, and thus improve performance and routability. Furthermore, the continuous increase of the problem size of IC routing is also a great challenge to existing routing algorithms. In this paper, we present the first multilevel framework for full-chip routing using the X-architecture. To take full advantage of the X-architecture, we explore the optimal routing for three-terminal nets on the X-architecture and develop a general X-Steiner tree algorithm based on the Delaunay triangulation approach for the X-architecture. The multilevel routing framework adopts a two-stage technique of coarsening followed by uncoarsening, with a trapezoid-shaped track assignment embedded between the two stages to assign long, straight diagonal segments for wirelength reduction. Compared with the state-of-the-art multilevel routing for the Manhattan architecture, experimental results show that our approach reduced wirelength by 18.7% and average delay by 8.8% with similar routing completion rates and via counts.

A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel

A bidirectional channel network-on-chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication. In a BiNoC, each communication channel allows to be dynamically self-reconfigured to transmit flits in either direction. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate. Novel on-chip router architecture is developed to support dynamic self-reconfiguration of the bidirectional traffic flow. This area-efficient BiNoC router delivers better performance and requires smaller buffer size than that of a conventional network-on-chip (NoC). The flow direction at each channel is controlled by a channel direction control (CDC) algorithm. Implemented with a pair of finite state machines, this CDC algorithm is shown to be high performance, free of deadlock, and free of starvation. Extensive cycle-accurate simulations using synthetic and real-world traffic patterns have been conducted to evaluate the performance of the BiNoC. These results exhibit consistent and significant performance advantage over conventional NoC equipped with hard-wired unidirectional channels.