Ying Ruan

Energy and thermal aware mapping for mesh-based NoC architectures using multi-objective ant colony algorithm

Where IP cores to be mapped must be carefully solved for any given application in order to optimize different performance metrics in Network-on-Chip (NoC) design flow. The optimization of different performance metrics simultaneously may cause a negative effect on each other because of the strong correlation between these performance metrics. In this paper, we propose a multi-objective ant colony algorithm (MOACA) that maps IP cores onto mesh-based NoC architectures. This algorithm is an efficient way to find the pareto-optimal front which optimizes energy consumption and hotspot temperature of NoC. The algorithm has been implemented and evaluated for synthetic generated benchmarks. Experimental results confirm the efficiency, accuracy and scalability of the algorithm.

New heuristic algorithms for low-energy mapping and routing in 3D NoC

Three Dimensional Network on Chip 3D NoC, which reduces the average number of hops traversed by a packet, can achieve better performance than the traditional 2D NoC. However, when routers deliver packets in 3D NoC, more energy consumption is needed. High-energy consumption and small packaging density will cause excessive heat, which increases vulnerability of the system in performance and reliability. In this paper, we present a low-energy consumption mapping algorithm based on the symmetry of the architecture and construct a deadlock-free routing algorithm using mapping result information. Our proposed algorithms can reduce the total energy consumption of communication and achieve a good system performance under the bandwidth constraints. To evaluate the efficacy of the algorithms, we perform experiments on several benchmarks and compare the proposed algorithms with other existing algorithms. Experimental results show that, for complex benchmarks, our proposed algorithms get better results than others.

A high linearity SiGe BiCMOS power amplifier for 2.4GHz wireless communications

A high linearity power amplifier (PA) is demonstrated for wireless communications at 2.4 GHz and is implemented in a 0.18um Silicon Germanium (SiGe) BiCMOS process. This PA is composed of two stages and achieves a good performance on linearity: when the input power is 0dBm, the output 1dB compression point (OP1dB) is 20.3dBm, which is only about 0.7dBm less than the output power. The layout area of this PA is 1.1×1.3mm2.

A Fully Integrated SiGe BiCMOS Power Amplifier for 2.4GHz Wireless-LAN Application

A 2.4GHz power amplifier (PA) for Wireless-LAN application is designed and implemented in 0.18µm SiGe BiCMOS technology. Without any off-chip component or band wire for matching, the proposed power amplifier is fully integrated, which has a two-stage structure with temperature-insensitive biasing circuit to improve the linearity with almost no increase in die area. S parameter simulation results show that input impedance matching S11 and output impedance matching S22 is less than -13dB and -20dB respectively. The power amplifier has a power gain of 27.3dB, output 1dB compression point of 23.2dBm, and a power added efficiency(PAE) of 21.3%.The area of the die is 1148×1140µm2 with all elements integrated on a single chip.

A 2.4GHz monolithic SiGe power amplifier for Wireless-LAN transceiver

A high-linearity power amplifier (PA) for 2.4GHz Wireless-LAN transceiver is presented. The PA is designed and implemented using a 0.18um SiGe BiCMOS process. An on-chip adaptive linearizer is comprised of a base-emitter diode of the bias transistor and a bypass capacitor with almost no increase in die area and no extra dc consumption. Besides the linearization function, the active biasing circuit is also temperature-insensitive with simple structure. Including all matching circuits and biasing circuits, the die area of the fully integrated PA is 1.2mm∗1.1mm. Temperature simulation indicates the variation of power gain is less than 1.6dB from 20°C to 80°C. The second-order and third-order LMD are less than −30.9dBc and −34.5dBc when the output PI dB has been reached. With 3.3 V supply, the PA achieves max PldB of 23.2dBm and a power added efficiency (PAE) of 21.3%