Yinghong Tian

An multi-rate LDPC decoder based on ASIP for DMB-TH

Based on ASIP (Application Specific Instruction Set Processor), this paper propose a decoder architecture for LDPC (Low Density Parity Check Codes) in the DMB-TH standard. The decoder use a five-stage pipeline, 32-bit RISC processor and it can supports three different code rates (0.4, 0.6 and 0.8) by only modifying the program. Based on XC4VLX150, at the max frequency of 126 MHz, the max throughput of the decoder can achieve 96Mps for 10 TDMP-decoding Iterations. Compared with other GPP and DSP implementations, this ASIP simplify the control logical and enhance the flexibility1.

Uniform All-Integer Quantization for Irregular LDPC Decoder

In this paper, we present a uniform all-integer quantization for irregular LDPC decoder. The LLR values at the variable nodes and the check nodes are mapped to integer with their integer part of their value directly. Variable nodes are quantized to 6-bit integer and check nodes are quantized to 4-bit integer after the input channel messages are scaled up, and at a given iteration number the messages are scaled down. A lookup table is used to store the configuration parameters for quantization, and the hardware architecture of quantization is proposed. Simulations of (3048,7493) show the performance is better than the floating point in normalized min-sum and close to floating point in offset min-sum. The uniform all-integer quantization is easy to be implemented and does not require the floating point operations and so reduces the hardware complexity and lower power.

An ASIP encoder for Quasi-Cyclic LDPC codes

This paper proposes a LDPC (Low Density Parity Check Codes) encoder architecture for DMB-TH based on ASIP (Application Specific Instruction Set Processor). The encoding algorithm is first analyzed and optimized for the ASIP encode, And then the special instruction sets are extracted according to the optimized algorithm. The ASIP architecture uses main processor and coprocessor to get high throughput. This ASIP encoder can support three different code rates (0.4, 0.6 and 0.8) just by different programs and thus is more flexible than other ASIC implementations. Based on XC2V6000, at the max frequency of 117MHz, the max throughput of the encoder can deliver 187Mbps, 206Mbps and 232Mbps for 0.4, 0.6 and 0.8 code rates, respectively.

A LDPC decoder with all single port memories

this paper proposes one LDPC decoder with all single port memories to lower requirements of logic and interconnection and save hardware cost. Considering the lower read-write speed of single port memories than that of dual port memories, the decoder needs to reduce computation complex and shorten the critical path delay so as to get high throughput. To get the purpose, the LDPC decoder uses TDMP algorithm and normalized MS algorithm to reduce computation complex, uses reusable and configurable CVPU to realize single cycle pipeline variable and check node updating calculation, uses optimized shuffle network to shorten the path delay, and uses memories dominated controller to avoid the read and write conflict of memories. The implementation results show for once iteration process the throughputs are about 890Mbps, 847Mbps, and 863Mbps for rate 0.4, 0.6, and 0.8 respectively.

An Efficient Memory System for Fast Block Matching Motion Estimation Algorithms

This paper proposes an efficient memory system (MS) for fast block matching motion estimation algorithms, which suffer from bandwidth problem and random block data access problem. One novel data-to-memory mapping algorithm is proposed to solve these problems. By data reuse and efficient memory arrangement based on Latin Square, the bandwidth can be reduced to 5.15Mbit/s for SVGA video. To balance better between I/O Pads and bandwidth, the proposed MS uses 8 pixel data input. The proposed MS also proposes tree-type 2 to 1 multiplex shuffle networks and address offset method to reduce delay and optimize the implementation. The FPGA-base implementation can work at 227MHz clock and meet real-time requirements in the SVGA video system with VBSME. Keywords-Motion estimation; memory system; data reuse;