Yingmei Chen

A 38 Gb/s to 43 Gb/s Monolithic Optical Receiver in 65 nm CMOS Technology

A scaled 40 Gb/s optical receiver incorporating a transimpedance amplifier (TIA), a limiting amplifier (LA), a clock and data recovery (CDR), and a 1:4 demultiplexer was proposed in 65 nm CMOS technology. The TIA employs a regulated cascode structure to achieve low input resistance and a stable dc operating point, whereas the LA adopts the third-order interleaving active feedback technique to obtain greater bandwidth and flatter frequency response. A 10 GHz LC-based voltage controlled oscillator with a ring structure that generates eight phases is presented. A quarter-rate phase detector in the CDR samples the 40 Gb/s input data, which are retimed and demultiplexed into four sets of 10 Gb/s output data. Experimental results show that the recovered clock exhibits a phase noise of -112.39 dBc/Hz@10 MHz from a carrier frequency of 10 GHz, in response to 231-1 PRBS input. The retimed and demultiplexed data exhibit a peak-peak jitter of 4.46 ps and an RMS jitter of 1.18 ps. The core circuit of the receiver consumes 160 mW from a 1.2 V supply.

A 10 GHz multiphase LC VCO with a ring capacitive coupling structure

A multiphase LC voltage-controlled oscillator (VCO) with a novel capacitive coupling CL ladder filter structure is proposed in this paper and this 10 GHz eight-phase VCO is applied in clock and data recovery (CDR) circuit for 40 Gb/s optical communications system. Compared with the traditional eight-phase oscillator, this capacitive coupling structure can decrease the number of inductors to half and only of four inductors. The VCO is designed and taped out in TSMC 65 nm CMOS technology. Measurement results show the phase noise is 105.95 dBc/Hz at 1MHz offset from a carrier frequency of 10 GHz. The chip area of VCO is 480 μm×700 μm and the VCO core power dissipation is 4.8 mW with the 1.0 V supply voltage.

Design of low power 4×40 Gb/s laser diode driver for parallel optical transmission systems

Compared with conventional electrical interconnection technology, optical interconnection has the merits of anti-interference, small signal loss, long transmission distance and so on. Furthermore, parallel optical interconnects become the crucial technique to solve the problem of large capacity data transmission in high-speed transmission systems. The parallel mode can decrease transmit rate of every optical fiber, reduce the demands for optical devices and decrease the cost of optical interconnects [1–3]. Optical transmitter chip which consists of a multiplexer and a laser diode driver (LDD), is the crucial module for the optical fiber communication system. The LDD is used to amplify the output signal of multiplexer and turn the electrical signal into optical one. The bipolar transistor of SiGe BiCMOS technology has higher operating frequency and superior driving ability, so many high-speed LDDs are designed in SiGe BiCMOS [4, 5]. Ref. [4] has relatively large output swing, but it consumes more power of 3600 mW. The large power consumption is not suitable for high-density optical interconnects. Using low-power bandwidth enhancement techniques, a 40 Gb/s VCSEL driver IC is successfully developed in 180-GHz SiGe BiCMOS technology in [5]. But the passive peaking inductors in output stage occupy large chip area, which cannot retain 250 μm channel space for parallel optical transmission. A 4-channel 40 Gb/s parallel VCSEL driver array in GF 0.13 μm SiGe BiCMOS technology is proposed in this article. The pre-emphasis technique of RC parallel negative feedback makes it acquire high operating rate and occupy small chip area. Circuit design. The function of VCSEL driver is to convert the electrical signal to optical one. Due to the driving signal of voltage or current, the VCSEL driver can be divided into current type driver and voltage type driver. This article proposed the voltage type driver because it is suitable for driving common-cathode type VCSEL. The structure of the 40 Gb/s laser diode driver consists of input buffer stage, pre-amplifier stage and output driver stage. The input buffer stage has three functions of impedance matching, DC bias, and voltage level shift. The 50 Ω impedance matching is designed to reduce the high frequency reflection of the signal, which goes through transmission line to the pads of chip. Pre-amplifier stage is located between the input buffer stage and the output driver stage, amplifying the signal to a large swing for the latter

4-channel, 40 Gb/s front-end amplifier for parallel optical receiver in 0.18 μm CMOS

This paper proposed a 4-channel parallel 40 Gb/s front-end amplifier (FEA) in optical receiver for parallel optical transmission system. A novel enhancement type regulated cascade (ETRGC) configuration with an active inductor is originated in this paper for the transimpedance amplifier to significantly increase the bandwidth. The technique of three-order interleaving active feedback expands the bandwidth of the gain stage of transimpedance amplifier and limiting amplifier. Experimental results show that the output swing is 210 mV (Vpp) when the input voltage varies from 5 mV to 500 mV. The power consumption of the 4-channel parallel 40 Gb/s front-end amplifier (FEA) is 370 mW with 1.8 V power supply and the chip area is 650 μm×1300 μm.

A Low-Jitter Full-Rate 25-Gb/s CDR for 100-Gb/s Optical Interconnects in 0.13-μm SiGe BiCMOS

ABSTRACT A low-jitter full-rate 25-Gb/s clock and data recovery (CDR) chip for 100-Gb/s optical interconnects is proposed. Fabricated in 0.13-μm SiGe BiCMOS technology, the chip is implemented in a third-order type-II bang-bang phase-locked loop (BBPLL) topology. To achieve optimal switching speed, all SiGe heterojunction bipolar transistors (HBTs) in high-speed blocks are biased at peak fT current density. Transistors are sized by carefully balancing speed versus power consumption. Emitter-coupled logic (ECL) and current-mode logic (CML) are employed in logic components. Compared with conventional spiral inductors, the employment of RF transmission lines in resonators of the VCO reduces the area of the VCO and, thus, the whole chip, without sacrificing the performance. The core circuits occupy an area of 0.48 mm2. The CDR recovers a clock with an rms jitter of 750 fs and a peak-to-peak jitter only of 3.46 ps.