Yinong Liu

Development of an Eight-Channel Time-Based Readout ASIC for PET Applications

An eight-channel readout ASIC has been developed for reading output signals from solid-state photomultipliers for positron emission tomography applications. This ASIC converts both the signal charge and occurring time to digital timing pulses so that only a time-to-digital converter is required for further signal processing. This provides the advantages of simplified circuit design, reduced power consumption, and suitability for applications that have a large number of readout channels. The ASIC uses a fully current mode preamplifier to achieve high bandwidth ( >; 100 MHz), high time resolution (better than ~ 1 ns FWHM), and low power consumption (a few mW/ch). The linear dynamic range of charge measurement is adjustable and can be extended up to 103 pC. The chip has been fabricated with 0.35 μm 2P4M CMOS technology. A test prototype board has been developed and used for ASIC functionality and performance evaluation. Our preliminary studies show that the targets have been successfully achieved.

A 20ps resolution wave union FPGA TDC with on-chip real time correction

Benefit from wave union, the bins (especially the ultra-wide bins) are sub-divided by each other, making FPGA TDC achieve a resolution beyond its cell delay. At such high level resolution, delay chain becomes very sensitive to the environment disturbance, including power supply voltage, temperature and current surge. On chip calibration needs lots of events and hence cannot follow fast delay changes of the chain. On-chip real time correction method proposed in this article gives one correcting parameter for each sample, making the FPGA TDC stronger when exposed to fast disturbance. A fast encoding logic is also implemented in our design and the dead time can be reduced to 1 clock cycle in the best case. Test results show a typical RMS of 20ps and the max RMS is below 30ps.

Design of a low noise readout ASIC for CdZnTe detector

A low noise readout ASIC has been designed for CdZnTe detector. This chip contains 16 channels and each channel consists of a dual-stage charge sensitive preamplifier, 4th order semi-Gaussian shaper, leakage current compensation circuit (LCC), discriminator and output buffer. This chip has been fabricated in Globalfoudries 0.35 μm CMOS process, the preliminary results are presented here. The total channel charge gain can be adjusted from 100 mV/fC to 400 mV/fC and the peaking time can be adjusted from 1 μS to 4 μS. The minimum ENC at zero input capacitance measured at maximum charge gain and 1.33 μS peaking time is 70 e. The noise difference between FR4 and PTFE test board are analyzed. When connected with a 4 × 4 pixelated CdZnTe detector, energy spectrum from radioactive isotope has been measured with energy resolution of 2.74 keY FWHM for 241Am.

On-Chip Real-Time Correction for a 20-ps Wave Union Time-To-Digital Converter (TDC) in a Field-Programmable Gate Array (FPGA)

The latest delay chain-based FPGA TDCs can achieve resolutions around 10 ps. At such high levels of accuracy, delay chains become very sensitive to parasitic electromagnetic perturbations, including power supply voltage, temperature, and current surge. This paper describes how common-mode fast perturbation can deteriorate the spectra and make the root mean square (RMS) periodical as the input time interval increases. Based on this observation, an on-chip real-time correction method can be implemented, giving a correcting reference for each sample. Results show a typical RMS of 20 ps, with a maximum value below 30 ps, under the perturbation of around 100 mV and 20 kHz coming from the DC-DC module.

Single-Event Multiple Transients in Conventional and Guard-Ring Hardened Inverter Chains Under Pulsed Laser and Heavy-Ion Irradiation

Single-event multiple transients (SEMTs) are investigated using an on-chip self-triggered circuit. Measured results for inverter chains of two layout designs, including a guard-ring design and a conventional design, are compared under pulsed laser and heavy-ion (Bi) irradiations. Pulsed laser exposures of different energies and Bi heavy-ion irradiation at different injection angles, including along the well direction and across the well direction, are found to produce SEMTs with different probabilities. The use of a guard-ring hardening technique is demonstrated to be very effective in reducing production of SEMTs for inverters without direct electrical connection. Charge sharing-induced SEMTs are found to have different pulsewidth distributions for angled ion incidence than normal ion or laser incidence.

Quantitative analysis and efficiency study of PSD methods for a LaBr3:Ce detector

Abstract The LaBr 3 :Ce scintillator has been widely studied for nuclear spectroscopy because of its optimal energy resolution ( 3 :Ce is a critical issue, and pulse shape discrimination (PSD) has been shown to be an efficient potential method to suppress the alpha background from the 227 Ac. In this paper, the charge comparison method (CCM) for alpha and gamma discrimination in LaBr 3 :Ce is quantitatively analysed and compared with two other typical PSD methods using digital pulse processing. The algorithm parameters and discrimination efficiency are calculated for each method. Moreover, for the CCM, the correlation between the CCM feature value distribution and the total charge (energy) is studied, and a fitting equation for the correlation is inferred and experimentally verified. Using the equations, an energy-dependent threshold can be chosen to optimize the discrimination efficiency. Additionally, the experimental results show a potential application in low-activity high-energy γ measurement by suppressing the alpha background.

Development of a 64-Channel Readout ASIC for an

In this paper, we developed a 64-channel application specific integrated circuit (ASIC) named EXYT for 8 × 8 SSPM arrays for positron emission tomography (PET) and time-of-flight (TOF)-PET applications. It integrates individual fast readout for timing and resistive networks for energy and position measurements, which reduces the outputs down to 4 differential signals: Timing, Energy and X/Y positions. Gated summation circuits were implemented to suppress the dark count noise and to reduce the dead time. An automatic threshold calibration method was also introduced in this paper and the threshold difference among all the channels could be effectively reduced to <; 1 p.e. by adjusting a local 5-bit DAC for each channel. The chip has been fabricated with 0.18 μm CMOS technology. Evaluation system with SSPM array and LYSO crystals has been developed. All the functions of EXYT have been tested and verified. The power consumption is 3 mW per channel. Energy resolution of 12% and coincidence resolving time (CRT) of 363 ps (FWHM-full width at half maximum) have been achieved for 2 × 2 × 14 mm3 LYSO crystal(s). Sub-pixel resolution can be achieved when coupled to a 12 × 12 array of 2.7 × 2.7 × 14 mm3 LYSO crystals.

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Due to their high efficiency and high energy resolution, applications of CdZnTe (CZT) detectors have spread into many areas such as room temperature detectors. To improve the performance and decrease the effects of hole trapping and crystal non-uniformity, special contact geometries are applied to the detectors, such as Coplanar, 3D pixel, Frisch grid, Capture and so on. In this paper, we introduce a new line electrode geometry to greatly improve CZT detector performance. A line anode collects electrons, while a planar cathode collects holes. Due to the low electric field close to the cathode and the low hole μτ value, this geometry is also a single charge sensitive structure. The calculated energy resolution of a 20 mm x 20 mm x 15 mm detector could be improved up to 1.51% for 662 keV gamma rays. Both simulations and experimental results are presented here.

SSPM Array for PET and TOF-PET Applications

New time-based readout (TBR) electronics has been developed and evaluated for its performance and application for PET detectors. It consists of a leading edge (LE) timing threshold for timing pickoff that provides a signal timing t1; a charge integration followed by a constant discharge between two specific timings t2 and t3 that are used to directly measure the signal energy. The timing-walk error caused by LE from signals of different amplitudes can be measured with t1 as a function of different signal amplitudes that is proportional to the time difference between t2 and t3. With this pre-calibration, timing-walk error can be accurately corrected. Therefore, both signal timing and energy can be accurately measured with digital timing signals without using CFD and ADC. These timing signals were controlled and in principle can be measured by an FPGA that can apply many signal logic and data correction algorithms. A single channel discrete component TBR circuit has been implemented in PC board, and 8-channel ASIC chips have been developed for feasibility evaluations and PET detector applications. Initial functionality and performance evaluations have been conducted. Signal amplitude measurement accuracy and linearity are very good; the measured timing accuracy from a pulse is the same as a standard CFD and reaches to ∼100 ps resolution with the test setup. Both suitable energy and coincidence timing resolutions (∼17% and ∼1.0–2.0 ns) were achieved with PMT or Solid-State PM (SSPM) array based PET detectors. Initial studies to acquire flood source crystal identification map has demonstrated the advantages of applying parallel readout with TBR electronics that read out and process signals from each pixel of SSPM array independently. With its relatively simple circuit and low cost, TBR electronics is expected to provide suitable front-end signal readout electronics for compact photon detectors such as SSPM array that require large number of output channels and demand high performance in energy and timing.

PERFORMANCE IMPROVEMENT OF CZT DETECTORS BY LINE ELECTRODE GEOMETRY

An eight-channel readout ASIC has been developed for reading out signals from Silicon Photomultiplier (SiPM) for PET applications. It converts both signal charge and occurring time to digital timing pulses and only needs TDC. It has the advantages of simplified circuit design, reduced power consumption and suitable for large number of readout channels. The ASIC uses a fully current mode preamplifier to obtain high bandwidth (>100MHz) with a few mW/ch power consumption. The dynamic range for charge measurement is adjustable and can be extended up to 103 pC. The chip has been fabricated in 0.35μm 2P4M CMOS technology. A test prototype board for ASIC evaluation has been developed and the preliminary tests show the time jitter is 150ps (rms) by electronics only with injected 30 ns rise time signals, and the coincidence timing is about 1.7 ns (FWHM) for 511 keV photo peak events with LYSO/SiPM detectors. The charge dynamic range is measured to be ∼10bit for electronics only, and better than 1% for detector signals. A simple theoretic analysis shows that the timing and charge resolutions are limited dominately by the detector dark noise in our test and will be studied further. Preliminary evaluations show that the ASICs functionalities and performance targets have been successfully achieved.