Lunyao Wang

An Integrated Optimization Approach for Nanohybrid Circuit Cell Mapping

This paper presents an integrated optimization approach for nanohybrid circuit (CMOS/nanowire/molecular hybrid) cell mapping. The method integrates Lagrangian relaxation and memetic search synergistically. Based on encoding manipulation with appropriate population and structural connectivity constraints, 2-D block crossover, mutation, and self-learning operators are developed in a concerted way to obtain an effective mapping solution. In addition, operative buffer insertion is performed to leverage the quality of routing. Numerical results from ISCAS benchmarks and comparison with previous methods demonstrate the effectiveness of the modeling and solution methodology. The method outperforms the previous work in terms of CPU runtime, timing delay, and circuit scale.

CMOL cell assignment by genetic algorithm

We present a genetic algorithm for cell assignment of CMOL, a hybrid CMOS/molecular circuit architecture. We introduce a two dimensional block partially mapped crossover operator as well as mutation operator for our genetic algorithm and conducted experiments using the ISCAS benchmarks. Empirical results indicate our method has faster CPU runtime, has better (more compact) area utilization, and can handle much larger benchmarks than prior methods.

A Memetic Approach for Nanoscale Hybrid Circuit Cell Mapping

The article presents the principle of operation of a coupled three-phase reactor (CTRλ) used applied in 18-pulse diode converter. Using sets of coupled three-phase power network reactors, the presented converter makes it possible to considerably reduce, at low cost, undesired higher harmonics in the power network current. Selected results of laboratory tests done on a 20kVA 18-pulse diode converter are included.This paper considers a cell mapping task of CMOL, a hybrid CMOS/molecular circuit architecture. To tackle the combinatorial hurdle arising from the structural connectivity domain constraint, a memetic computing algorithm is developed. The framework takes advantage of simulated annealing based local search strategy and appropriate population based encoding manipulation. Numerical results from ISCAS benchmarks and comparison with pure genetic approach illustrate the effectiveness of the modeling and solution methodology. In terms of CPU runtime, timing delay and circuit scale, the proposed method has better performance than previous methods.

Cell Mapping for Nanohybrid Circuit Architecture Using Genetic Algorithm

Nanoelectronics constructed by nanoscale devices seems promising for the advanced development of integrated circuits (ICs). However, the lack of computer aided design (CAD) tools seriously hinders its development and applications. To investigate the cell mapping task in CAD flow, we present a genetic algorithm (GA) based method for Cmos/nanowire/MOLecular hybrid (CMOL), which is a nanohybrid circuit architecture. By designing several crossover operators and analyzing their performance, an efficient crossover operator is proposed. Combining a mutation operator, a GA based algorithm is presented and tested on the International Symposium on Circuits and Systems (ISCAS) benchmarks. The results show that the proposed method not only can obtain better area utilization and smaller delay, but also can handle larger benchmarks with CPU time improvement compared with the published methods.

CMOL cell assignment based on dynamic interchange

A new method based on dynamic interchange for cell assignment task of CMOL, a hybrid integrated circuit architecture, is proposed. In this paper, we first transform AND/OR/NOT gates composed of logic circuits into NOT gates and two inputs NOR gates, and then map the NOR/NOT gates to CMOL cells. During mapping process, we first allocate adequate CMOL cell resources and then randomly map the gates to the CMOL cells, which can satisfy the architecture demand and require no overlap between cells. Then we adjust the gates by interchanging and inserting buffers for long distance gate pair. Experiment results on MCNC benchmark show that the proposed approach can result in faster running time than prior approaches1.

Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergence

With the ever-increasing power demands of consumer electronics and portable devices, multi-supply voltage (MSV) technique is supposed as one of the direct and effective ways for power optimization in SoC designs. To realize MSV implementation, procedures such as voltage assignment, voltage island partitioning and level shifters (LSs) placement should be considered simultaneously during the floorplanning stage. Although many works addressed the MSV-driven design problem, few of them actually took account of LS placement, which makes the generated results may limit the potential applications. Furthermore, existing design frameworks are often very computationally expensive, and it is not beneficial to shorten the time to market. In this paper, we present an MSV-driven SoC floorplanning framework for fast design convergence. Several techniques are proposed and integrated into an efficient and flexible non-randomized floorplanning algorithm. Firstly, to reserve the desired deadspace for the placement of LSs, the netlist is modified by assigning virtual LSs in the nets. Secondly, a heuristic based voltage assignment method is presented for accuracy and execution time trade-off. Thirdly, different from previous works which do voltage assignment without physical information feedback, an inner loop is built between voltage assignment and LS placement under the constraints of both timing and physical layout. Experimental results on Gigascale Systems Research Center (GSRC) benchmark suites indicate the proposed approach can improve power saving by 12%, CPU time by 48% with 4% area increase. HighlightsA heuristic-based voltage assignment algorithm is proposed for accuracy and CPU time balance.Virtual LSs are assigned in the netlist to reserve the required deadspace for LS placement.Voltage assignment and LS placement are operated iteratively to satisfy timing and physical constraints.The proposed algorithms are integrated into a highly efficient floorplanning algorithm for fast design convergence.

Level shifter planning for timing constrained multi-voltage SoC floorplanning

To implement multi-voltage technique in SoC designs, level shifters (LSs) are essential modules which translate signals among different voltage domains. However, inserting LSs requires non-negligible area and timing overhead. In this paper, we study LS planning (LSP) method for timing constrained multi-voltage SoC floorplanning problem. The design flow consists of two phases. In phase I, to reserve the desired white space for the placement of LSs, the netlist is modified by assigning virtual LSs in the nets. In phase II, the main floorplanning loop is implemented. Different from previous works which do voltage assignment without physical information feedback, we build an inner loop between voltage assignment and LS placement under the constraints of both timing and physical layout. Experimental results on Gigascale Systems Research Center (GSRC) benchmark suites indicate the proposed approach can improve power saving by 15% with 4% area increase.

Voltage Drop Aware Power Pad Assignment and Floorplanning for Multi-voltage SoC Designs

Multi-voltage technique is an effective way of power saving in system-on-a-chip (SoC) designs. However, as the technology nodes continue to shrink, the voltage drop constraint in multiple power domains presents serious obstacles in power/ground (P/G) network design of wire-bonding package. In this paper, a voltage drop aware power pad assignment and floor planning method for multi-voltage SoC designs is proposed. In order to reduce the voltage drop, we develop a fast method to calculate the location of power pad for each power domain based on the spring model. During floor planning iterations, a static voltage drop analysis is performed to update the voltage drop distribution, and then number of violation nodes in the P/G network is obtained. To speed up the floor planning algorithm, instead of time-consuming matrix computation to obtain voltage drops, we use the weighted distance from blocks to power pads as an optimization objective. Experimental results on GSRC benchmark suites indicate that the proposed approach generates an optimized placement of power pads and floor planning of blocks.

Low Power State Assignment Algorithm for FSMs Considering Peak Current Optimization

Finite state machine (FSM) plays a vital role in the sequential logic design. In an FSM, the high peak current which is drawn by state transitions can result in large voltage drop and electromigration which significantly affect circuit reliability. Several published papers show that the peak current can be reduced by post-optimization schemes or Boolean satisfiability (SAT)-based formulations. However, those methods of reducing the peak current either increase the overall power dissipation or are not efficient. This paper has proposed a low power state assignment algorithm with upper bound peak current constraints. First the peak current constraints are weighted into the objective function by Lagrangian relaxation technique with Lagrangian multipliers to penalize the violation. Second, Lagrangian sub-problems are solved by a genetic algorithm with Lagrangian multipliers updated by the subgradient optimization method. Finally, a heuristic algorithm determines the upper bound of the peak current, and achieves optimization between peak current and switching power. Experimental results of International Workshop on Logic and Synthesis (IWLS) 1993 benchmark suites show that the proposed method can achieve up to 45.27% reduction of peak current, 6.31% reduction of switching power, and significant reduction of run time compared with previously published results.

Timing-driven logic restructuring for nano-hybrid circuits

As the feature size of the integrated circuits (ICs) scales down, the future of nano-hybrid circuit looks bright in extending Moores Law. However, mapping a circuit to a nano-fabric structure is vexing due to connectivity constraints. A mainstream methodology is that a circuit is transformed into a nano-fabric preferred structure by buffer insertion to high fan-out gates. However, it may result in timing degradation. Logic replication is a traditional way to split high fan-out gates in logic synthesis but may not be suitable for high fan-out gates with high fan-ins. In this article, a timing-driven logic restructuring framework at the gate level is proposed. The proposed framework identifies the high fan-out gates from a given gate netlist according to the fan-out threshold, following by the restructuring of high fan-out gates through the application of logic replication and buffer insertion. To improve circuit timing from a global perspective, latent critical edges are identified to avoid entrapping critical paths during the restructuring. Experimental results on ISCAS benchmarks indicate that 8.51% timing improvement and 6.13% CPU time reduction can be obtained traded with 4.16% area increase on an average.