Yipeng Huang

Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time

We present a unit that performs continuous-time hybrid approximate computation, in which both analog and digital signals are functions of continuous time. Our 65 nm CMOS prototype system is capable of solving nonlinear differential equations up to 4th order, and is scalable to higher orders. Nonlinear functions are generated by a programmable, clockless, continuoustime 8-bit hybrid architecture (ADC + SRAM + DAC). Digitally assisted calibration is used in all analog/mixed-signal blocks. Compared to the prior art, our chip makes possible arbitrary nonlinearities and achieves 16× lower power dissipation, thanks to technology scaling and extensive use of class-AB analog blocks. Typically, the unit achieves a computational accuracy of about 0.5% to 5% RMS, solution times from a fraction of 1 μs to several hundred μs, and total computational energy from a fraction of 1 nJ to hundreds of nJ, depending on equation details. Very significant advantages are observed in computational speed and energy (over two orders of magnitude and over one order of magnitude, respectively) compared to those obtained with a modern microcontroller for the same RMS error.

Continuous-Time Hybrid Computation with Programmable Nonlinearities

We present the first continuous-time hybrid computing unit in 65nm CMOS, capable of solving nonlinear differential equations up to 4th order, and scalable to higher orders. Arbitrary nonlinear functions used in such equations are implemented by a programmable clockless continuous-time 8b hybrid architecture (ADC+SRAM+DAC) with activity-dependent power dissipation. We also demonstrate the use of the unit in a low-power cyber-physical systems application.

Evaluation of an analog accelerator for linear algebra

Due to the end of supply voltage scaling and the increasing percentage of dark silicon in modern integrated circuits, researchers are looking for new scalable ways to get useful computation from existing silicon technology. In this paper we present a reconfigurable analog accelerator for solving systems of linear equations. Commonly perceived downsides of analog computing, such as low precision and accuracy, limited problem sizes, and difficulty in programming are all compensated for using methods we discuss. Based on a prototyped analog accelerator chip we compare the performance and energy consumption of the analog solver against an efficient digital algorithm running on a CPU, and find that the analog accelerator approach may be an order of magnitude faster and provide one third energy savings, depending on the accelerator design. Due to the speed and efficiency of linear algebra algorithms running on digital computers, an analog accelerator that matches digital performance needs a large silicon footprint. Finally, we conclude that problem classes outside of systems of linear equations may hold more promise for analog acceleration.

Analog Computing in a Modern Context: A Linear Algebra Accelerator Case Study

Approaching the post-Moores law era, researchers are looking for scalable ways to get useful computation from existing silicon technology. This article presents a programmable analog accelerator for solving systems of linear equations. The authors compensate for commonly perceived downsides of analog computing, such as low precision and accuracy, limited problem sizes, and difficulty applying it to different workloads. On the basis of a prototyped analog accelerator chip, they compare the analog solvers performance and energy consumption against an efficient digital algorithm running on a general-purpose processor. The analog accelerator approach is 10 times faster and provides 33 percent energy savings. Owing to the speed and efficiency of linear algebra algorithms running on digital computers, an analog accelerator that matches digital performance needs a large silicon footprint, which limits scalability. The authors conclude that problem classes outside of systems of linear equations could hold more promise for analog acceleration.

RoboBench: Towards sustainable robotics system benchmarking

We present RoboBench, a novel platform for sharing robot full-system simulations for benchmarking. The creation of this platform and benchmark suite is motivated by a need for reproducible research. A challenge in creating a full-system benchmarks are incompatibilities in software created by different groups and the difficulty of reproducing software environments. We solve this problem by using software containers, an emerging virtualization technology. RoboBench enables sharing robot software in a runnable state, capturing the software behavior of robots carrying out missions. These simulations make clear the performance impact and resource usage of programs and algorithms relative to other software involved in the mission. These containers are integrated with the CITK platform for reproducible research, which automates generation and publishing of the containers. We present an overview of the system, a description of our prototype set of benchmark missions, along with a validation study comparing the computational load profile of a mission performed on a real and simulated robot. Additionally, we present preliminary results of an overall analysis of the benchmarks in the RoboBench suite, showing where computational work is expended in robotics common robotics tasks. RoboBench is extensible, and is the first step toward a robust, quantitative approach to engineering computationally-efficient robots.

Hybrid analog-digital solution of nonlinear partial differential equations

We tackle the important problem class of solving nonlinear partial differential equations. While nonlinear PDEs are typically solved in high-performance supercomputers, they are increasingly used in graphics and embedded systems, where efficiency is important. We use a hybrid analog-digital computer architecture to solve nonlinear PDEs that draws on the strengths of each model of computation and avoids their weaknesses. A weakness of digital methods for solving nonlinear PDEs is they may not converge unless a good initial guess is used to seed the solution. A weakness of analog is it cannot produce high accuracy results. In our hybrid method we seed the digital solver with a high-quality guess from the analog side. With a physically prototyped analog accelerator, we use this hybrid analog-digital method to solve the two-dimensional viscous Burgers’ equation—an important and representative PDE. For large grid sizes and nonlinear problem parameters, the hybrid method reduces the solution time by

Hybrid Continuous-Discrete Computer: from ISA to Microarchitecture

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Trustworthy hardware from untrusted components

116CCS CONCEPTS•Computer systems organization → Analog computers; Heterogeneous(hybrid)systems; • Hardware → Application specific integrated circuits; • Mathematics of computing → Nonlinear equations; Partial differential equations;

Corrections to “Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time”

In this project, we design an instruction set architecture for a proposed hybrid continuous-discrete computer (HCDC) chip. The ISA harnesses the microarchitectural features and analog circuitry provided in the hardware. We describe the workloads that are suitable for the HCDC architecture. The underlying microarchitecture for the HCDC chip, including its controllers, datapaths, and interfaces to analog and digital functional units are specified in detail. We live in a world that is continuous: our eyes see scenes defined by continuous curves and intensities of colors, hear sounds formed by continuously varying pressure waves, and we sense velocity and temperature as continuous signals. In contrast, current computers operate in a discrete world, despite the continuous nature of the world at the scale our senses perceive. We finely divide time and space into quanta in order to model the real world on our digital computers. The inherent costs of digital computing have been acceptable because of digital computers exponential growth in computing power relative to energy consumption and size. However, as scaling in digital computers comes to an end, we must explore alternatives to digital, discrete computing.