Yong-Bin Kim

CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits

This paper presents a novel design of ternary logic gates using carbon nanotube (CNT) FETs (CNTFETs). Ternary logic is a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. A resistive-load CNTFET-based ternary logic design has been proposed to implement ternary logic based on CNTFET. In this paper, a novel design technique for ternary logic gates based on CNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs. Especially, the proposed ternary logic gate design technique combined with the conventional binary logic gate design technique provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier. Extensive simulation results using SPICE are reported to show that the proposed ternary logic gates consume significantly lower power and delay than the previous resistive-load CNTFET gates implementations. In realistic circuit application, the utilization of the proposed ternary gates combined with binary gates results in over 90% reductions in terms of the power delay product.

A novel CNTFET-based ternary logic gate design

This paper presents a novel design of ternary logic inverters using carbon nanotube FETs (CNTFETs). Multiple-valued logic (MVL) circuits have attracted substantial interest due to the capability of increasing information content per unit area. In the past extensive design techniques for MVL circuits (especially ternary logic inverters) have been proposed for implementation in CMOS technology. In CNTFET device, the threshold voltage of the transistor can be controlled by controlling the chirality vector (i.e. the diameter); in this paper this feature is exploited to design ternary logic inverters. New designs are proposed and compared with existing CNTFET-based designs. Extensive simulation results using SPICE demonstrate that power delay product is improved by 300% comparing to the conventional ternary gate design.

Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems

In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the adaptive optimal reverse body-bias voltage. The adaptive optimal body-bias voltage is generated from the proposed leakage monitoring circuit, which compares the subthreshold current (I SUB) and the band-to-band tunneling (BTBT) current (I BTBT). The proposed circuit was simulated in HSPICE using 32-nm bulk CMOS technology and evaluated using ISCAS85 benchmark circuits at different operating temperatures (ranging from 25°C to 100°C). Analysis of the results shows a maximum of 551 and 1491 times leakage power reduction at 25°C and 100°C, respectively, on a circuit with 546 gates. The proposed approach demonstrates that the optimal body bias reduces a considerable amount of standby leakage power dissipation in nanoscale CMOS integrated circuits. In this approach, the temperature and supply voltage variations are compensated by the proposed feedback loop.

A CMOS subbandgap reference circuit with 1-v power supply voltage

A CMOS subbandgap reference circuit with 1-V supply voltage is described. To obtain subbandgap reference voltages with a 1-V supply voltage, threshold voltage reduction and subthreshold operation techniques are used. Large /spl Delta/V/sub BE/ (100 mV) as well as a 90-dB operational amplifier are used to circumvent the amplifier offset. A power-on-reset (POR) circuit is used as startup. This circuit has been implemented using a standard 0.5-/spl mu/m CMOS process, and its size is 940 /spl mu/m/spl times/1160/spl mu/m. The temperature coefficient is 17 ppm from -40/spl deg/C to 125/spl deg/C after resistor trimming and the minimum power supply voltage is 0.95 V. The measured total current consumption is below 10 /spl mu/A and the measured output voltage is 0.631 V at room temperature.

Design of a Ternary Memory Cell Using CNTFETs

This paper presents a novel design of a ternary memory cell using carbon nanotube field-effect transistors (CNTFETs). Ternary logic is a promising alternative to conventional binary logic because it allows simplicity and energy efficiency in modern digital design due to the reduced circuit overhead in interconnects and chip area. In this paper, a novel design of a ternary memory cell based on CNTFETs is proposed; this cell uses a transmission gate for the write operation and a buffer for the read operation to make them separate. Chirality of the CNTFETs is utilized for threshold voltage control, thus avoiding the use of additional power supplies. Extensive simulation results using SPICE are reported to show that the two memory operations of the proposed ternary cell perform correctly at 0.9 V power supply. The static noise margin and read/write delay of the proposed ternary memory cell are also very good; by utilizing the latest CNTFET layout design tools, it is shown that the proposed ternary memory cell achieves a significant saving in area (41.6%) compared with its CMOS ternary counterpart at 32 nm.

Design of a CNTFET-Based SRAM Cell by Dual-Chirality Selection

This paper proposes a new design of a highly stable and low-power static RAM (SRAM) cell using carbon nanotube FETs (CNTFETs) that utilizes different threshold voltages for best performance. In a CNT, the threshold voltage can be adjusted by controlling the chirality vector (i.e., the diameter). In the proposed six-transistor SRAM cell design, while all CNTFETs of the same type have the same chirality, n-type and p-type transistors have different chiralities, i.e., a dual-diameter design of SRAM cell. As figures of merit, stability, power dissipation, and write time are considered when selecting the chirality for the best overall performance. A new metric, denoted as ¿SPR,¿ is proposed to capture these figures of merit. This metric shows that a CNTFET-based SRAM cell provides an ¿SPR¿ that is four times higher than for its CMOS counterpart that has the same configuration, thus attaining superior performance. Finally, the sensitivity of the CNTFET SRAM design to process variations is assessed and compared with its CMOS design counterpart. Extensive simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based SRAM cell due to variations in the diameter, supply voltage, and temperature of the CNTFETs. The CNTFET-based SRAM cell demonstrates that it tolerates the process, power supply voltage, and temperature variations significantly better than its CMOS counterpart.

A novel design methodology to optimize the speed and power of the CNTFET circuits

Carbon nanotubes with their superior properties have proved to be a potential alternative device to CMOS. In this paper, circuit optimization methods for high performance and low power CNFEFT circuit are proposed. The proposed design methods for CNTFET circuit address how to decide the optimum CNTFET parameters such as pitch, diameter, number of CNTs (Carbon Nano Tube), optimum fan-out factor and logical efforts to deliver the minimum power-delay product. The proposed method makes it possible to accomplish 56% dynamic power reduction and 22% less delay by optimizing the pitch, number of CNTs, fan-out factor, and logical efforts compared to the circuits that are not optimized and screening effects are ignored.

Performance evaluation of CNFET-based logic gates

As the physical gate length of current devices is reduced to below 65 nm, effects (such as large parametric variations and increase in leakage current) have caused the I-V characteristics to be substantially depart from those commonly associated with traditional MOSFETs, thus impeding the efficient development and manufacturing of devices at deep submicro/nano scales. Carbon Nanotube Field Effect Transistors (CNFETs) have received widespread attention, as one of the promising technologies for replacing MOSFETs at the end of the Technology Roadmap. This paper presents a detailed simulation-based assessment of circuit performance of this technology and compares it to conventional MOSFETs; the designs of different logic gates and the full adder circuit are simulated under the same minimum gate length and different operational conditions. It is shown that the power-delay product (PDP) and the leakage power for the CNFET based gates are lower than the MOSFET based logic gates by 100 to 150 times, respectively. The CNFET based logic gates demonstrate good functionality even at a 0.3 V power supply (while MOSFET based gates fail at 0.5 V).

Soft-Error Hardening Designs of Nanoscale CMOS Latches

As technology scales down in the deep sub-micron/nano ranges, CMOS circuits are more sensitive to externally induced phenomena to likely cause the occurrence of so-called soft errors. Therefore, the operation of these circuits to tolerate soft errors is a strict requirement in today’s designs. Traditional error tolerant methods result in significant cost penalties in terms of power, area and performance, and the development of low-cost hardened designs for storage cells (such as latches and memories) is of increasing importance. This paper proposes new hardened designs for CMOS latches at 32nm feature size. Three hardened latch circuits are proposed; two of these circuits are Schmitt trigger based, while the third one utilizes a cascode configuration in the feedback loop. These new hardened latches are shown to have superior performance in terms of power-delay product as well as highest tolerance to soft errors (measured by the critical charge) than existing hardened latches. Extensive simulation results are provided using the predictive technology file for 32nm feature size in CMOS.

A new SRAM cell design using CNTFETs

As CMOS devices scales to the nano ranges, increased short channel effects and process variations considerably affect device and circuit designs. Novel devices are been proposed to address these problems. As a promising new transistor, the carbon nanotube field effect transistor (CNTFET) avoids most of the fundamental limitations of the traditional CMOS devices. In this paper, the MOSFET-like CNTFET is reviewed and shown as a promising device for high-performance and low-power memory designs. A 6T SRAM cell based on CNTFET is designed and simulated to show the improvements in stability, performance, and sensitivity on process variations compared to the CMOS 6T SRAM design.