In-Seok Jung

Accurate and Efficient On-Chip Spectral Analysis for Built-In Testing and Calibration Approaches

The fast Fourier transform (FFT) algorithm is widely used as a standard tool to carry out spectral analysis because of its computational efficiency. However, the presence of multiple tones frequently requires a fine frequency resolution to achieve sufficient accuracy, which imposes the use of a large number of FFT points that results in large area and power overheads. In this paper, an FFT method is proposed for on-chip spectral analysis of multi-tone signals with particular harmonic and intermodulation components. This accurate FFT analysis approach is based on coherent sampling, but it requires a significantly smaller number of points to make the FFT realization more suitable for on-chip built-in testing and calibration applications that require area and power efficiency. The technique was assessed by comparing the simulation results from the proposed method of single and multiple tones with the simulation results obtained from the FFT of coherently sampled tones. The results indicate that the proper selection of test tone frequencies can avoid spectral leakage even with multiple narrowly spaced tones. When low-frequency signals are captured with an analog-to-digital converter (ADC) for on-chip analysis, the overall accuracy is limited by the ADCs resolution, linearity, noise, and bandwidth limitations. Post-layout simulations of a 16-point FFT showed that third-order intermodulation (IM3) testing with two tones can be performed with 1.5-dB accuracy for IM3 levels of up to 50 dB below the fundamental tones that are quantized with a 10-bit resolution. In a 45-nm CMOS technology, the layout area of the 16-point FFT for on-chip built-in testing is 0.073 mm2, and its estimated power consumption is 6.47 mW.

A CMOS Low-Power Digital Polar Modulator System Integration for WCDMA Transmitter

This paper presents a novel low-power design and highly cost effective chip implementation solution of digital polar modulator for WCDMA transmitters using 0.35 μm mixed mode CMOS technology. The proposed coordinate rotation digital computer (CORDIC) in the polar modulator converts rectangular coordinate to polar coordinate with significantly less hardware and power comparing to the existing computational intensive algorithm by employing hard wired pipeline strategy to increase the performance and to reduce the hardware size. The proposed CORDIC performs a sequence of elementary rotations using shift and add operations without multiplications, providing a highly cost effective solution. The separate distribution of angle constants to each adder permits a hard-wire solution instead of using a lookup table, and all the shifters are hard-wired. Linear interpolators to extend the sampling rate for WCDMA specification are used to decrease the operating frequency. The proposed approach reduces both size and power by integrating booth CORDIC and power amplifier on the same die. The measured average power consumption is 27 mW with 67 MHz clock and 3 V power supply.

A novel sort error hardened 10T SRAM cells for low voltage operation

In this paper, two types of a soft error hardened 10T SRAM cells with high static noise margin (SNM) are proposed for low voltage operation. The proposed NMOS stacked SRAM cell operates normally with higher read SNM near to sub-threshold region compared to prior works. Simulated results using 0.18um standard CMOS process demonstrate that proposed NMOS stacked-10T cell has high read SNM and high soft error resilience of at least 100 times higher than unprotected standard 6T SRAM cell for a single event transient (SET).

The novel Switched-Capacitor DC-DC converter for fast response time and reduced ripple

A novel voltage regulation scheme to control the number of multi-phase and frequency for Switched-Capacitor(SC) DC-DC converters is presented. The controller adjusts the number of interleaved phases with the size of switches. In addition, switching frequency of SC DC-DC converter is increased to reduce output ripple voltage when output load current is low. 16phase 2∶1 SC DC-DC converter is designed in 45nm standard CMOS process using the proposed scheme. The converter with new control technique achieves fast response and low Vout ripple under fast varying currents. Maximum output voltage ripple(Vripple) is less than 15mV and maximum response time is less than 0.2us with 4mA. Normal Vripple is less than 2mV.

A built-in calibration system to optimize third-order intermodulation performance of RF amplifiers

A digital built-in calibration (BIC) system is presented to automatically adjust the linearity performance of a tunable RF low-noise amplifier (LNA) operating at 2.4GHz. An envelope detection circuit is used to extract the linearity characteristics at low frequencies, enabling the sampling and digital signal processing at low rates. The output of the envelope detector is digitized before the spectrum calculation with an integrated fast Fourier transform (FFT) for estimation of the third-order intermodulation (IM3) distortion specification of the LNA. The digitally-assisted closed-loop calibration scheme is demonstrated with simulations using a two-tone test with 1MHz tone spacing, a 512-point FFT engine, a 10-bit analog-to-digital converter model, and digital blocks operating with a 51.2MHz clock frequency. The total calibration time is 485μs. The digital blocks were implemented using a standard 0.13μm CMOS technology.

A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch

This paper presents a low-power 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input with a novel Built-in Self Calibration (BiSC) feature to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as fore-ground operation so that low power consumption is achieved. Consequently, the mismatch error of the DAC can be minimized and the SAR based ADC operates without any extra power dissipation for the circuitry of self calibration during normal operation. The prototype was designed using 0.13μm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.2 dB and consumes 3.57 mW with 1.2V supply voltage and sampling rate of 32 MS/s. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 45% and 51%, respectively.

A novel self-calibration scheme for 12-bit 50MS/s SAR ADC

This paper presents a low-power 12-bit 50MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using single input condition for Built-In Self Test (BIST) that uses a novel self-calibration scheme to reduce both offset voltage of a comparator and capacitor mismatch of the DAC. The proposed self-calibration scheme changes the offset voltage of the comparator continuously for every step to decide onebit code. The changed offset voltage of the comparator is able to cancel not only inherent offset voltage of the comparator but also the mismatch of DAC. Consequently, the total mismatch error of both the comparator and capacitor of DAC can be reduced. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 47% and 52%, respectively. The prototype was designed using 0.13μm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.6 dB and consumes 4.62 mW. The ADC core occupies an active area of only 240μm×298μm Using 1.2V supply and the sampling rate of 50 MS/s,.

A built-in calibration system with a reduced FFT engine for linearity optimization of low power LNA

A digital built-in calibration (BIC) system with a power and area optimized on-chip fast Fourier transform (FFT) engine is presented to automatically adjust the linearity of a tunable RF low-noise amplifier (LNA) operating at 2.4GHz. An envelope detection circuit is used to extract the linearity characteristics at low frequencies, enabling the sampling and digital signal processing at low rates. To compensate the low gain of an envelope detector and to enhance reliability of spectral analysis, an RF amplifier is designed between the LNA and the envelope detector. The output of the envelope detector is digitized before the spectrum calculation with the integrated FFT for estimation of the third-order intermodulation (IM3) distortion specification of the LNA. The digitally-assisted closed-loop calibration scheme is demonstrated with simulations using a two-tone test with 1MHz tone spacing, a 512-point FFT engine, a 10-bit analog-to-digital converter model, and digital blocks operating with a 51.2MHz clock frequency. The total time required for calibration is 485μs including delays of 1.2μs to allow settling of the LNA output after capacitor array changes for tuning. In order to validate the proposed BIC technique with device mismatch effects, Monte Carlo simulations are performed with the same condition at transient simulations, where the results are well matched with the optimum IM3 component values calculated at the output node of LNA. The digital blocks were implemented using a standard 0.13μm CMOS technology.

A 10-bit 64MS/s SAR ADC using variable clock period method

This paper presents a low-power 10-bit 64MS/s successive approximation register (SAR) analog-to-digital converter (ADC) for Built-In Self Test (BIST) that uses a monotonic capacitor switching and variable clock period method for single input condition. To achieve high speed, a non-fixed clock time technique is used to reduce not only peak current but also die area. The technique removes conversion time waste and extends the SAR operation speed over 64MHz easily. Compared to the converters that use the conventional procedure, maximum peak current and DAC drivers area are reduced by about 33.8% and 25.2%, respectively. Single input ADC generally limits the resolution unlike the differential input ADC. However, the proposed ADC in this paper achieves high resolution and accuracy with a single input signal. The prototype was designed using 0.13μm single poly 6 metal standard CMOS technology. Using 1.2V supply and the sampling rate of 64 MS/s, the ADC achieves a SNDR of 50.2 dB and consumes 1.325 mW. The ADC core occupies an active area of only 185μm×210μm.

A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration

A 100MS/s 10-bit ADC design using a 130nm standard CMOS technology is presented in this paper. The proposed design adopted the split capacitor array digital-to-analog converter (DAC) to build successive approximation register (SAR) analog-to-digital converter (ADC) structure using a single input. On-chip mismatch calibration feature is utilized to compensate the capacitor mismatches of the DAC and to calibrate the input offset voltage of a comparator. The proposed calibration uses a simple and efficient algorithm and optimizes the capacitor mismatches of the DAC by using inverter-based capacitor comparison technique and by controlling additional auxiliary capacitor arrays in calibration mode. The ADC achieves 41.9dB of SNR and consumes 1.1mW with 1.2V supply voltage.