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Dive into the research topics where Yong-Il Kwon is active.

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Featured researches published by Yong-Il Kwon.


IEEE Transactions on Circuits and Systems | 2012

An Ultra Low-Power CMOS Transceiver Using Various Low-Power Techniques for LR-WPAN Applications

Yong-Il Kwon; Sang-Gyu Park; Ta-Joon Park; Koon-Shik Cho; Hai-Young Lee

In this work, we implemented and evaluated a fully integrated 2.4 GHz CMOS RF transceiver using various low-power techniques for low-rate wireless personal area network (IEEE 802.15.4 LR_WPAN) applications in 0.18-μm CMOS technology. In order to achieve an ultra low power consumption, a RC oscillator (OSC) operating below 200 nA, a regulator operating below 200 nA for sleep mode, a quick start block for the crystal oscillator, a passive wake-up circuit, a LNA with negative gm, a current bleeding mixer, and a stacked VCO are all implemented in this transceiver. The transmitter achieves less than 5.0% error vector magnitude (EVM) at 5 dBm output, and the receiver sensitivity is -101 dBm. The sensitivity of the wake-up block is -29.8 dBm. The current consumption is below 14.3 mA for the data receiving mode, 16.7 mA for the transmitter, and less than 600 nA for the sleep mode from a 1.8 V power supply. That is considered to be lowest for the 2.4 GHz CMOS ZigBee transceiver compared to open literature results.


international conference on sensing technology | 2008

A CMOS temperature sensor with calibration function using band gap voltage reference

Dong-Ok Han; Yong-Il Kwon; Tahjoon Park; Heon-Chul Park

In this paper, an accurate temperature sensor was implemented using 0.18 mum CMOS technology. The temperature sensor which was designed with the bandgap reference circuit is calibrated by trimming common mode voltage of an operational amplifier. The temperature sensor can compensate for other blocks of the IC chip above the special temperature when the ADC was a power off for low power operation. It consumes only 365 muA with a 3 V supply voltage. This temperature sensor can be calibrated up to a maximum 7 degree. And the average error is -0.8degC in sensing range from -30degC to 90degC in comparison with simulation result.


asia-pacific microwave conference | 2006

A fully integrated 2.4 GHz IEEE 802.15.4 transceiver for Zigbee applications

Joonhyung Lim; Koon-Shik Cho; BoyLe Seo; Yong-Il Kwon; WooSang Lee; KwangMook Lee; Myeungsu Kim; SangHyun Min; Tahjoon Park

This single-chip RF and modem transceiver provides a complete radio interface between the radio block, digital demodulation including time and frequency synchronization and data buffering. The number of external components is minimized so that only one crystal and one resistor and several decoupling capacitors are required. The bidirectional differential antenna pins are commonly used for RX and TX, therefore, no external antenna switch is needed. One on chip low-drop voltage regulator provides the analog and digital 1.8 V supply. The RX and TX signal processing part is implemented using 0.18 mum libraries, utilizing the low power consumption and the high density of the technology. The transceiver is implemented in a 1P6M 0.18 mum CMOS Technology with MIM capacitors. The receiver sensitivity is -94.7dBm for 1% packet error rate defined in IEEE 802.15.4 standard and error vector magnitude (EVM) of transmitter is 10% for 2.4 GHz band.


radio frequency integrated circuits symposium | 2006

14-mW 5-GHz frequency synthesizer with CMOS logic divider and phase-switching dual-modulus prescaler

Myeungsu Kim; Ta-Joon Park; Yong-Il Kwon; Joonhyung Lim; Sang-Gyu Park; Sung-Han Kim

A 5-GHz frequency synthesizer for Zigbee (IEEE 802.15.4) was implemented. It consumes only 14mW adopting CMOS logic divider and phase-switching dual-modulus. A 2nd loop filter is internally embodied to reduce external components. The phase switching is made between the 45deg spaced output phases to reduce the power consumption and improve the robustness of circuit. This synthesizer was fabricated in 0.18-mum technology; it consumes 8mA at 1.8V and offers 100kHz-loop bandwidth and -103dBc/Hz at an offset of 1MHz. the lock time is 30mus. The PLL output tuning range is 11% from 2.37GHz to 2.66GHz


radio frequency integrated circuits symposium | 2010

A fully integrated 2.4-GHz CMOS diversity receiver with a novel antenna selection

Yong-Il Kwon; Sang-Ku Park; Tahjoon Park; Hai-Young Lee

A new low-complexity antenna diversity architecture, using a 2.4-GHz single low-IF receiver chain with a novel antenna selection scheme, is exploited by using 0.18-µm CMOS technology. The receiver has been developed for the IEEE standard 802.15.4 radio system and two RF input channels are selected through an efficient analog-type antenna selection scheme for achieving the diversity. Compared to conventional receivers without diversity, 10∼15 dB improvement of the received signal strength (RSS) has been measured for non-line-of-sight (NLOS) channels. By incorporating a wake-up function for the baseband blocks, the receiver operates at a very low power of 8.5 mW, with a 1.8 V power supply in the standby mode for receiving. The antenna selection error is negligible (≪1 %) and the antenna selection time is very fast (≪20 µs).


IEEE Microwave and Wireless Components Letters | 2008

A 9 mW Highly-Digitized 802.15.4 Receiver Using Bandpass

Yong-Il Kwon; Ta-Joon Park; Koon-Shik Cho; Hai-Young Lee

A low power (9 mW) highly-digitized 2.4 GHz receiver for sensor network applications (IEEE 802.15.4 LR-WPAN) is realized by a 0.18 mum CMOS process. We adopted a novel receiver architecture adding an intermediate frequency (IF) level detection scheme to a low-power complex fifth-order continuous-time (CT) bandpass SigmaDelta modulator in order to digitalize the receiver. By the continuous-time bandpass architecture, the proposed SigmaDelta modulator requires no additional anti-aliasing filter in front of the modulator. Using the IF detector, the achieved dynamic range (DR) of the overall system is 95 dB at a sampling rate of 64 MHz. This modulator has a bandwidth of 2 MHz centered at 2 MHz. The power consumption of this receiver is 9.0 mW with a 1.8 V power supply.


radio frequency integrated circuits symposium | 2007

\Sigma\Delta

Myeungsu Kim; Kwengmook Lee; Yong-Il Kwon; Joonhyung Lim; Ta-Joon Park

A 5-GHz frequency synthesizer for ZIGBEE(IEEE 802.15.4) was implemented. It consumes 13.5 mW adopting CMOS Logic divider and robust VCO from process and temperature variation by body voltage control of current source. It incorporates an automatic capacitor-bank tuning loop to extend frequency tuning range. This synthesizer was fabricated in 0.18-um technology; it consumes 7.5 mA at 1.8 V and offers 100 kHz-loop bandwidth and always -103 dBc/Hz at an offset of 1 MHz. the lock time is 30 us. The PLL output tuning range is 14% from 2.258 GHz to 2.614 GHz.


Journal of electromagnetic engineering and science | 2007

ADC and IF Level Detection

Yong-Il Kwon; Sang-Woon Jung; Hai-Young Lee

In this paper, a low-power 2.4 ㎓ front-end for sensor network application (IEEE 802.15.4 LR-WPAN) is designed in a 0.18 um CMOS process. A power supply circuit with a novel temperature-compensation scheme is presented. The simulation and measurement results show that the front-end (LNA, Mixer) can achieve a voltage gain of 35.3 ㏈ and a noise figure(NF) of 3.1 ㏈ while consuming 5.04 mW (LNA: 2.16 mW, Mixer: 2.88 mW) of power at 27 ℃. The NF includes the loss of BALUN and BPF. The low-IF architecture is used. The voltage gain, noise figure and third-order intercept point (IIP3) variations over ?45 ℃ to 85 ℃ are less than 0.2 ㏈, 0.25 ㏈ and 1.5 ㏈, respectively.


Journal of electromagnetic engineering and science | 2008

5-GHz Frequency Synthesizer With Auto-Calibration Loop

Yong-Il Kwon; Ta-Joon Park; Hai-Young Lee

A low power(9 ㎽) highly-digitized 2.4 ㎓ receiver for sensor network applications(IEEE 802.15.4 LR-WPAN) is realized by a 0.18 ㎛ CMOS process. We adopted a novel receiver architecture adding an intermediate frequency (IF) level detection scheme to a low-power complex fifth-order continuous-time(CT) bandpass ΣΔ modulator in order to digitalize the receiver. By the continuous-time bandpass architecture, the proposed ΣΔ modulator requires no additional anti-aliasing filter in front of the modulator. Using the IF detector, the achieved dynamic range(DR) of the overall system is 95 ㏈ at a sampling rate of 64 ㎒. This modulator has a bandwidth of 2 ㎒ centered at 2 ㎒. The power consumption of this receiver is 9.0 mW with a 1.8 V power supply.


international conference on thermal, mechanical and multi-physics simulation and experiments in microelectronics and microsystems | 2010

A Low-Power 2.4 GHz CMOS RF Front-End with Temperature Compensation

Changsung Sean Kim; Jongpa Hong; Jihye Shim; Yongsun Won; Yong-Il Kwon

A multiphysics modeling and design has been performed for the worlds largest Metal Organic Vapor Phase Epitaxy (MOVPE) reactor by combining Theory of Inventive Problem Solving (TRIZ) for concept design, Design for Six Sigma (DFSS) for shape optimization, and Computer-Aided Engineering (CAE) simulations of multi-scale from atomic to macro scales. Numerical simulations considering gas phase chemical reactions and surface chemistry have been thoroughly verified by comparing with experimental measurements from various MOVPE reactors. As a preliminary study, two transparent mock-up models for the ultra-large MOVPE reactor were made in real scale and their internal flow fields were measured by laser Doppler velocimetry (LDV). A RF induction heater was also simulated by coupling the thermo-fluid field and electro-magnetic field together. Since the MOVPE reactor was manufactured, numerous tests for high-temperature reliability and temperature uniformity have repeatedly been conducted. Consequently, these multidisciplinary approaches have been successfully applied to develop the ultralarge MOVPE reactor for group III-nitride light emitting diode (LED).

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Tahjoon Park

Samsung Electro-Mechanics

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Han-Jin Cho

Samsung Electro-Mechanics

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