Yongfu Li

A 2.89-μW clockless wireless dry-electrode ECG SoC for wearable sensors

This paper presents a clockless fully-integrated wireless electrocardiogram (ECG) system-on-chip (SoC) for wearable ECG sensor. The clockless implementation is enabled by the combination of event-driven ADC and impulse-radio ultra-wideband transmitter, leading to an order of magnitude reduction in power. A DC-coupled analog front-end with a novel baseline stabilizer boosts the input impedance to several GΩ, which minimizes the impact of motion artifacts and facilities the dry-electrode based ECG recording. An on-chip antenna increases the system integration level and makes flexible patch possible. Implemented in 0.13 μm CMOS technology, the entire system consumes 2.89 μW under 1.2 V supply when transmitting raw ECG data.

A 0.45-to-1.2-V Fully Digital Low-Dropout Voltage Regulator With Fast-Transient Controller for Near/Subthreshold Circuits

A low quiescent current digital low-dropout (DLDO) voltage regulator with fast-transient response time is proposed for self-powered wireless sensor applications operating at near/subthreshold supply voltage. The D-LDO regulator incorporates both hill-climbing and binary search algorithms (HCBS) in the control logic, thus leveraging on each others strengths to minimize the output voltages ripple and the quiescent current during the steady-state period as well as output voltages spike and response time during the transition period. Additional features such as hysteresis mode control and freeze mode control are incorporated into the system to improve the performance of the D-LDO regulator. A dynamic comparator is proposed for the near/subthreshold supply voltage operation, which minimizes the voltage error and improves the maximum operating frequency. Fabricated in 130-nm CMOS technology, the D-LDO regulator regulates the output voltage VOUT from 350 to 1150 mV, while the input supply voltage VIN ranges from 450 to 1200 mV. At a VOUT of 450 mV, VIN of 500 mV and an operating frequency of 10 MHz, the regulator delivers 1500-μA load current with IQUIESCENT of 8.9 μA and a transient response time of 1.6 μs. The maximum current and power efficiencies reach 99.9% and 89.9%, respectively. The measured line regulation and load regulation are 1.6 and 0.6 mV/mA, respectively.

A 2.89

This paper presents a fully integrated wireless electrocardiogram (ECG) SoC implemented in asynchronous architecture, which does not require system clock as well as off-chip antenna. Several low power techniques are proposed to minimize power consumption. At the system level, a newly introduced event-driven system architecture facilitates the asynchronous implementation, thus removes the system clock leading to a true ECG-on-chip solution. A DC-coupled analog front-end is introduced together with a baseline stabilizer to boost the input impedance to 3.6 GQ and mitigate the electrode offset, which is less sensitive to motion artefact and contact impedance imbalance, making it well suited for dry-electrode based applications. Level-crossing analog-to-digital converter (LC-ADC) is employed to take the advantage of burst nature of ECG signal leading to at least 5 times reduction in sampling points compared to Nyquist sampling. A digitally implemented impulse-radio ultra-wideband transmitter is seamlessly integrated with LC-ADC and an on-chip antenna for wireless communications. Implemented in 0.13 μm CMOS technology, the ECG-on-chip consumes 2.89 μW under 1.2 V supply while transmitting the raw ECG data, which attains one order of magnitude lower than the current state-of-the-art designs. The fully integrated ECG SoC requires no external clocks and off-chip antenna, making it a good candidate for low cost and disposable wireless ECG patches, such as epidermal electronics.

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This paper presents the design of a modified StrongArm regenerative comparator in 0.13-μm CMOS technology, operating at a supply voltage of 200-mV. The comparator uses a pair of cross-coupled P-type transistors to replace the conventional cross-coupled inverters, improving the comparison time and voltage headroom. A robust S-R latch is proposed to solve the race condition which occurs when the S-R latch enters a forbidden state especially during ultra-low supply voltage operation. As a result, the circuit shows up to 1.8× voltage offset reduction and 73% less sensitivity in the delay per input voltage difference (delay/log(ΔVIN)), which is about 65ns/decade, compared to conventional latched comparators.

W Dry-Electrode Enabled Clockless Wireless ECG SoC for Wearable Applications

In this paper, we proposed an improved true random number generator (TRNG), which comprises a low-bias hardware random number generator (HRNG) and a scrambler based on linear-feedback shift register (LFSR). The HRNG reduces both DC offset from the noise sources and offset voltage from the comparator to generate low-bias bitstream. The LFSR-based scrambler further reduces the bias to zero without sacrificing the throughput rate. Randomness quality is verified by Monte Carlo simulations using the randomness test suite.

An ultra-low voltage comparator with improved comparison time and reduced offset voltage

This work presents a clockless frequency-shift keying (FSK) receiver based on asynchronous architecture for epidermal electronics. The proposed architecture is free from system clock, adaptive to wide range of data rates and capable of duty-cycling. It makes use of continuous-time analog-to-digital converter (ADC) and signal processing techniques to improve the power efficiency. Implemented in 65-nm digital CMOS process, the simulation shows that the receiver works at the data rates ranging from 1.2-kbps to 100-kbps while consuming 120-μW to 1962-μW for a carrier frequency of 433.5-MHz.

Zero-bias true random number generator using LFSR-based scrambler

To design high-resolution and high-speed current-steering digital-to-analog converter (DAC), both amplitude and timing mismatches should be minimized. In this paper, a dynamic mapping method based on the combination of magic-square-mapping (MSM) and random-segment-selection (RSS) is proposed to improve the performance of DAC. A design example of 12-bit 500-MS/s current-steering DAC is used to illustrate the advantages of the proposed dynamic mapping method. The design is verified by the Monte Carlo simulation, which attains more than 90dB SFDR across the Nyquist bandwidth.

A clockless FSK receiver architecture with scalable data rate for epidermal electronics

In this chapter, we present two key designs for ultra-low-power electrocardiography sensors, i.e., an event-driven analog-to-digital converter (ADC) and an on-off keying (OOK) transceiver. For the ADC, two QRS detection algorithms, pulse-triggered (PUT) and time-assisted PUT (t-PUT), are proposed based on the level-crossing events generated from the ADC. For the transceiver SoC, we propose a novel supply isolation scheme to avoid the instability induced by such a high receiver gain, use bond wires as inductors to reduce the transmitter power, and utilize near-threshold design (NTD) method for low power digital baseband. Fabricated in 0.13 \(\upmu \mathrm{m}\) CMOS technology, the ADC with QRS detector consumes only 220 nW measured under 300 mV power supply, making it the first nanoWatt compact analog-to-information (A2I) converter with embedded QRS detector. The transceiver SoC is fully integrated with a 10 Mb/s transceiver, digital processing units, an 8051 micro-controlled unit (MCU), a successive approximation (SAR) ADC, and etc. The receiver consumes 0.214 nJ/bit at − 65 dBm sensitivity, and the Tx energy efficiency is 0.285 nJ/bit at an output power of − 5. 4 dBm. In addition, the digital baseband consumes 34.8 pJ/bit with its supply voltage lowered to 0.55 V, indicating its energy per bit is reduced to nearly 1/4 of the super-threshold operation.