Yong-Sik Kwak

A 1.1 V 82.3dB audio ΔΣ ADC using asynchronous SAR type quantizer

A switched-capacitor second-order audio ΔΣ analog-to-digital converter (ADC) is presented. The proposed ΔΣ ADC employs low-distortion input feed-forward architecture to relax the linearity requirement of the integrators. A 4-bit asynchronous successive approximation register (SAR) type internal quantizer is used for power efficient design by incorporating the analog adder with the quantizer. A tree-structured dynamic element matching (DEM) technique is employed to reduce the distortion resulted from the capacitor mismatch in the feedback digital-to-analog converter (DAC). The prototype ΔΣ ADC implemented in a 45nm CMOS process achieves 85.4 dB peak signal-to-noise ratio (SNR), 82.3 dB peak signal-to-noise and distortion ratio (SNDR) and 98.1 dB dynamic range (DR) for a signal bandwidth of 24 kHz while consuming 517.4 μW at 1.1 V supply voltage.

A 1.0 V 77.5 dB Dynamic Range Delta-sigma ADC using Op-Amp Bias Sharing Technique

A second-order single-bit delta-sigma analog-to-digital converter (ADC) is presented in this paper. An op-amp bias sharing technique is used to reduce the power consumption and active area of the ADC. It achieves 77.5 dB dynamic range over 1 kHz signal bandwidth with an oversampling ratio of 512. The total power consumption of the proposed ADC is 27.1 mW from a 1.0 V power supply. The prototype chip occupies 0.16 mm using a 0.13 mm CMOS technology.

An analog front-end for self-capacitance touch sensing with environmental noise reduction technique

A differential analog front-end (AFE) circuit for self-capacitance touch screen panel (TSP) is described. It receives two pseudo-differential signals from a panel to cancel out common environmental noises. Each pseudo-differential input signal is achieved by using up and down charge-pumps which convert self-capacitances of two adjacent channels into voltages. The dc signal resulted from the proposed capacitance-to-voltage converter is cancelled out by summing the two differential inputs which have opposite polarity dc levels. It enables the use of high gain amplifier which results in enhanced sensitivity.

A 1.8 V 89.2 dB Dynamic Range Delta-Sigma Modulator Using An Op-Amp Dynamic Current Biasing Technique

A third-order single-bit delta-sigma modulator is presented in this paper. An op-amp dynamic current biasing technique is used to improve the power-efficiency of the modulator. The voltage reference block is integrated with the delta-sigma modulator core to avoid the use of large off-chip bypass capacitors and to minimize pin numbers. It achieves 89.2 dB dynamic range over 10 kHz signal bandwidth with an oversampling ratio of 128. The delta-sigma modulator core and on-chip voltage reference block consume 880μW and 550μW, respectively, from a 1.8V power supply. The prototype chip occupies 1.26mm2 using a 0.18 μm CMOS technology.

A 10-bit 20-MS/s dual-channel algorithmic ADC with improved clocking scheme

A 10-bit 20-MS/s dual-channel algorithmic analog-to-digital converter (ADC) using an improved clocking scheme is presented. The proposed ADC employs amplifier sharing technique with a conversion time scaling to reduce area and power. To achieve further improvement of conversion time scaling, dedicated MDAC sampling capacitors scaled with the accuracy requirement of each cycle are used. The ADC implemented in a 0.18μm CMOS process achieves 59.6dB SFDR and 54.3dB SNDR while consuming 8.96 mW per channel from a 1.8-V supply voltage.

A 12-bit 200-kS/s SAR ADC with hybrid RC DAC

A 12-bit 200-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented. A sample-and-hold amplifier (SHA) is employed to convert single-ended input signal into fully-differential signal. The proposed SAR ADC exploits VCM-based switching method with a hybrid RC digital-to-analog converter (DAC) to reduce the size of the capacitive DAC. A three-stage preamplifier followed by a latch is employed for a comparator to avoid the metastability problem and achieve high accuracy comparison. The prototype ADC fabricated in a 0.18 μm CMOS process shows the measured DNL and INL within 0.48 LSB and 0.76 LSB, respectively. The ADC shows the maximum SNDR and SFDR of 64.2 dB and 80.4 dB with a 2.8 V supply while consuming 1.16 mW. It occupies an active die area of 0.25 mm2.

A 1.8 V 89.2 dB delta-sigma adc for sensor interface with on-chip reference

A switched-capacitor (SC) third-order single-loop single-bit delta-sigma analog-to-digital converter (ADC) for sensor interface is presented. The ADC is integrated on the same chip with a bandgap reference. To reduce the power consumption, opamp bias current switching technique is adopted. The prototype delta-sigma ADC fabricated in a 0.18μm CMOS process achieves 89.2 dB dynamic range (DR), 77.1 dB signal-to-noise ratio (SNR) and 77.0 dB signal-to-noise and distortion ratio (SNDR) over 10 kHz signal bandwidth with an over-sampling-ratio (OSR) of 128. The total power consumption is 1.42 mW at 1.8 V supply.