Yongchul Song

Quadrature direct digital frequency synthesizers using interpolation-based angle rotation

This paper describes a quadrature direct digital frequency synthesizer (QDDFS) architecture based on a new phase-to-sine conversion technique. The proposed technique uses polynomial interpolation and rotational transformation in a fine/coarse approach, achieving high-resolution output with a wide spurious-free dynamic range (SFDR). The QDDFS with this technique requires small-sized lookup tables and a simple computational engine. The fine/coarse decomposition significantly reduces the size of required lookup tables, and the polynomial interpolation enables accurate approximation of cosine and sine values. Two prototype QDDFS ICs were fabricated in 0.35-/spl mu/m CMOS. The final prototype IC produces 16-b cosine and sine outputs with a spectral purity greater than 100-dB. It has a frequency tuning resolution of 0.03-Hz at a 150-MHz sampling rate and consumes 350-mW with a 3.0-V power supply.

A 14-b direct digital frequency synthesizer with sigma-delta noise shaping

This paper describes a 14-b direct digital frequency synthesizer (DDFS) utilizing a sigma-delta noise shaping technique to reduce spurs arising from phase truncation. A new phase accumulator architecture adopting a second-order sigma-delta modulator is proposed. The sigma-delta noise shaping eliminates periodicity inherent in the phase truncation error. With the proposed phase accumulator, the significant spurs are reduced, and the spectral characteristics of the DDFS are then determined by finite precision of sine-amplitude output. A prototype DDFS IC in 0.25-/spl mu/m CMOS was fabricated on 0.12-mm/sup 2/ die area. The measured spurious-free dynamic range (SFDR) is greater than 110 dB for 16-b phase value and 14-b sine-amplitude output. The fabricated IC consumes 100 mW with a 2.5-V supply, and correctly operates up to 250 MHz.

A 250MHz direct digital frequency synthesizer with /spl Sigma//spl Delta/ noise shaping

A 14b direct digital frequency synthesizer in 0.25/spl mu/m CMOS uses a 2b second-order /spl Sigma//spl Delta/ modulator. The /spl Sigma//spl Delta/ noise shaping significantly reduces spurs caused by phase truncation and the measured SFDR is >110dB. The prototype IC consumes 100mW with a 2.5V supply and works to 250MHz.

A 300mW programmable QAM transceiver for VDSL applications

A complete VDSL CAM transceiver including ADC, DAC, clock generator, and micro-controller interface, fabricated in 0.18/spl mu/m 1P 6M CMOS technology is described. A new IIR notch filter and dual loop AGC are incorporated in the design. Total power consumption is 300mW and the IC supports a 13Mb/s data rate over a 9000 ft distance with a BER < 10/sup -7/.

A 16 b quadrature direct digital frequency synthesizer using interpolative angle rotation algorithm

A quadrature direct digital frequency synthesizer (DDFS) is fabricated in 0.35 /spl mu/m CMOS using a new phase-to-sine conversion algorithm. It achieves a spurious-free dynamic range (SFDR) of 96 dB with small-sized lookup tables and appropriate arithmetic hardware. The prototype DDFS IC generates 16 b cosine and sine outputs with an output frequency tuning resolution of 0.03 Hz. It works at 150 MHz sampling rate, consuming 670 mW.

Symbol timing recovery using digital spectral line method for 16-CAP VDSL system

This paper presents a new digital spectral line symbol timing recovery method for 16-CAP VDSL system. The proposed method resolves the digital implementation issues of the analog counterpart in two ways: (i) it avoids the costly linear phase bandpass filter that would otherwise be necessary, and (ii) it resolves the bandwidth expansion problem by using a single-sided pre-filter pair. With the architectural simplicity, its lower-frequency sampling clock offers an inexpensive implementation for the high speed timing recovery. Simulation shows that the jitter performance of the proposed method approaches to the theoretical limit especially for the transmission distance of less than 200 meters.

Low-jitter digital timing recovery techniques for CAP-based VDSL applications

In this paper, a digital timing recovery technique for carrierless amplitude and phase modulation (CAP)-based very-high-speed digital subscriber line (VDSL) applications is presented. A digital spectral line method is proposed for the timing tone extraction. It avoids the bandwidth expansion normally caused by the nonlinear property of the timing tone extraction block, and lowers the required sampling clock frequency. Also, an adaptive loop gain control scheme is proposed to reduce the timing jitter, simultaneously achieving both fast locking and low steady-state jitter. A prototype timing recovery circuit in a 0.35-/spl mu/m CMOS technology achieves 12.02-ps and 86-ps rms and peak-to-peak jitter, respectively, at 40-MHz operation. This is equivalent to about 0.1% of the symbol rate, and suitable for VDSL applications. The prototype IC consumes about 55 mW with a 3.0-V power supply.

A 330-MHz 15-b quadrature digital synthesizer/mixer in 0.25-/spl mu/m CMOS

A quadrature digital mixer combined with a quadrature direct digital frequency synthesizer generates 15-b outputs from both 14-b inputs and internally synthesized carrier with a spectral purity greater than 100-dB. In this work, large-size tables for evaluating sine and cosine functions can be avoided by employing an interpolation-based fine/coarse vector rotation technique. The prototype IC fabricated in 0.25-/spl mu/m CMOS occupies 0.51mm/sup 2/ die area. it functions correctly up to 330-MHz, consuming 460-mW with a 2.5-V supply.

Digital timing synchronization with jitter reduction technique for cap-based VDSL system

This paper describes a digital timing synchronization method for the CAP-based VDSL system. An adaptive loop filter with digitally controlled loop gain is proposed for jitter performance improvement. The proposed loop filter allows both fast locking and low steady state jitter. A digital spectral line method is used for robust timing extraction. Simulation results show that RMS timing jitter is less than 0.4% of the symbol period even for the worst case channel and synchronization is established within 400 symbol periods. The VDSL system is implemented in a 0.6 /spl mu/m CMOS technology, and tested. The measured peak-to-peak timing jitter is about 0.1% of the symbol period, which makes the VDSL system receive data up to 52 Mbps over the telephone wire.

An Efficient Software-Defined Radio Architecture for Multi-Mode WCDMA Applications

This letter describes an efficient architecture for a Software Defined Radio (SDR) Wideband Code Division Multiple Access (WCDMA) receiver using for high performance wireless communication systems. The architecture is composed of a Radio Frequency (RF) front-end, an Analog-to-Digital Converter (ADC), and a Quadrature Amplitude Modulation (QAM) demodulator. A coherent demodulator, with a complete digital synchronization scheme, achieves the bit-error rate (BER) of 10-6 with the implementation loss of 0.5 dB for a raw Quadrature Phase Shift King (QPSK) signal.