Beomsup Kim

Analysis of timing jitter in CMOS ring oscillators

in this paper the effects of thermal noise in transistors on timing jitter in CMOS ring-oscillators composed of source-coupled differential resistively-loaded delay cells is investigated. The relationship between delay element design parameters and the inherent thermal noise-induced jitter of the generated waveform are analyzed. These results are compared with simulated results from a Monte-Carlo analysis with good agreement. The analysis shows that timing jitter is inversely proportional to the square root of the total capacitance at the output of each inverter, and inversely proportional to the gate-source bias voltage above threshold of the source-coupled devices in the balanced state. Furthermore, these dependencies imply an inverse relationship between jitter and power consumption for an oscillator with fixed output period. Phase noise and timing jitter performance are predicted to improve at a rate of 10 dB per decade increase in power consumption.<<ETX>>

A low-noise, 900-MHz VCO in 0.6-/spl mu/m CMOS

This paper describes a low-noise, 900-MHz, voltage-controlled oscillator (VCO) fabricated in a 0.6-/spl mu/m CMOS technology. The VCO consists of four-stage fully differential delay cells performing full switching. It utilizes dual-delay path techniques to achieve high oscillation frequency and obtain a wide tuning range. The VCO operates at 750 MHz to 1.2 GHz, and the tuning range is as large as 50%. The measured results of the phase noise are -101 dBc/Hz at 100-kHz offset and -117 dBc/Hz at 600-kHz offset from the carrier frequency. This value is comparable to that of LC-based integrated oscillators. The oscillator consumes 10 mA from a 3.0-V power supply. A prototype frequency synthesizer with the VCO is also implemented in the same technology, and the measured phase noise of the synthesizer is -113 dSc/Hz at 100-kHz offset.

A low-noise fast-lock phase-locked loop with adaptive bandwidth control

This paper presents a salient analog phase-locked loop (PLL) that adaptively controls the loop bandwidth according to the locking status and the phase error amount. When the phase error is large, such as in the locking mode, the PLL increases the loop bandwidth and achieves fast locking. On the other hand, when the phase error is small, this PLL decreases the loop bandwidth and minimizes output jitters. Based on an analog recursive bandwidth control algorithm, the PLL achieves the phase and frequency lock in less than 30 clock cycles without pre-training, and maintains the cycle-to-cycle jitter within 20 ps (peak-to-peak) in the tracking mode. A feed forward-type duty-cycle corrector is designed to keep the 50% duty cycle ratio over all operating frequency range.

On the use of linear programming for dynamic subchannel and bit allocation in multiuser OFDM

Adaptive subcarrier allocation and adaptive modulation for multiuser orthogonal frequency division multiplexing (OFDM) is considered. The optimal subcarrier and bit allocation problems, that have been formulated in Wong et al., (1999), and Rhee et al., (2000), as nonlinear optimizations, are converted into linear ones and solved by integer programming (IP). A suboptimal approach that separately performs subcarrier allocation and bit loading is proposed. It is shown that subcarrier allocation in this approach can be optimized by the linear programming (LP) relaxation of the IP. Comparison through computer simulation indicates that performance of the suboptimal approach can be close to that of the optimal.

PLL/DLL system noise analysis for low jitter clock synthesizer design

This paper presents an analytical model for timing jitter accumulation in ring-oscillator based phase-locked-loops (PLL). The timing jitter of the system is shown to depend on the jitter in the ring-oscillator and an accumulation factor which is inversely proportional to the bandwidth of the phase-locked-loop. Further analysis shows that for delay-locked-loops (DLL), which use an inverter delay chain that is not configured as a ring-oscillator, there is no noise enhancement since noise jitter events do not contribute to the starting point of the next clock cycle. Finally, theoretical predictions for overall jitter are compared to behavioral simulations with good agreement.<<ETX>>

A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme

A high-speed ring oscillator is proposed for improved operation frequency over those based on the conventional n-stage inverter chain. The ring oscillator consists of inverters with negative delay elements that are derived from the ring oscillator circuit. The cell delay of the ring oscillator is smaller than a fundamental inverter delay. Simulations show that the resulting operating frequencies are 50% higher than those obtainable from the conventional approaches.

A low-phase-noise CMOS LC oscillator with a ring structure

This LC ring oscillator is an architectural experiment to reduce the phase noise of an LC oscillator even further with a ring type structure. An LC oscillator with a special ring type structure performs phase noise filtering and attenuation. To prove the concept, several LC-ring oscillators are fabricated in 0.6 /spl mu/m, single-poly, triple-metal, CMOS. The three-stage LC-ring oscillator has -132 dBc/Hz measured phase noise at 600 kHz offset frequency from a 900 MHz carrier.

A low-noise phase-locked loop design by loop bandwidth optimization

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-/spl mu/m CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively.

A low-jitter mixed-mode DLL for high-speed DRAM applications

This paper presents a salient clock deskewing method with a mixed-mode delay-locked loop (MDLL) for high-speed synchronous DRAM applications. The presented method not only solves the resolution problem of conventional digital deskewing circuits, but also improves the jitter performance to the level of well-designed analog deskewing circuits, while keeping the power consumption and locking speed of digital deskewing circuits. The whole deskewing circuit is fabricated in a 3.3-V 0.6-/spl mu/m triple-metal CMOS process and occupies a die area of 0.45 mm/sup 2/. Measured rms jitter is 6.38 ps. The power consumption of the entire chip, including I/O peripherals, is 33 mW at 200 MHz with a 3.3-V supply.

A single-chip quad-band GSM/GPRS transceiver in 0.18 /spl mu/m standard CMOS

A 0.18 /spl mu/m CMOS single-chip fully integrated quad-band GSM/GPRS transceiver is presented. The low-IF receive section achieves -110dBm sensitivity at the antenna and -15dBm IIP3. The offset-frequency PLL transmitter achieves 1.2/spl deg/ rms phase noise, -65dBc modulation mask at 400kHz, and -165dBc/Hz noise at 20MHz. The chip occupies 17mm/sup 2/ and dissipates 95mA/112mA in receive/transmit mode.