Yongfeng Feng

Power-CAD: A novel methodology for design, analysis and optimization of Power Electronic Module layouts

Power Electronic Module (PEM) design requires simultaneous analysis of thermal, electrical, and mechanical parameters to design an optimal layout. The current design process being used by package designers involves a sequential procedure instead of a simultaneous process. Each design step involves the analysis of the thermal, electrical or mechanical aspects of the design. As a result, the designer has to iterate between the various design process steps in order to achieve an optimal design. This causes a substantial increase in the design cycle time. A new methodology has been developed and implemented in this work that helps to automate and optimize the PEM design process. Power-CAD uses an electrothermal simulation methodology, a parasitic extraction tool, and an optimization algorithm that helps to achieve an optimal layout for a discrete PEM. This approach promises to save time and money for the PEM design industry by significantly reducing the number of design cycles.

A survey of bottom-up behavioral modeling methods for analog circuits

This paper presents a brief on the current state-of-the-art in circuit modeling techniques that abstract reduced-order, higher-level models from the circuit or transistor level. The methods are reviewed in the context of the classes of circuits for which they have been demonstrated.

Impact of solid-state fault current limiters on protection equipment in transmission and distribution systems

Solid-state fault current limiters (SSFCLs) offer a number of benefits when incorporated within transmission and distribution systems. SSFCLs can limit the magnitude of a fault current seen by a system using different methods, such as inserting a large impedance in the current path or controlling the voltage applied to the fault. However, these two methods can introduce a few problems when SSFCLs are used in a system along with other protection equipment such as protective relays and sensors. An experiment was designed and implemented to evaluate the behavior of the protective relays in a mimic distribution system with a SSFCL. This paper introduces the details of the experiment and the result shows that the distorted current and voltage waveforms resulting from the action of the SSFCL disturb the protective equipment.

Certify— A characterization and validation tool for behavioral models

Device modeling plays an important role in VLSI circuit design because computer-aided circuit analysis results are only as accurate as the models used. This indicates a need for robust tools that can facilitate the testing, validation and characterization procedure of semiconductor device models. Certify, the graphical tool for model characterization and validation, is a step in this direction [1]. The software architecture and different modules of Certify have been described in this paper.

Ascend: automatic bottom-up behavioral modeling tool for analog circuits

This paper describes a new fully automated, behavioral modeling tool, Ascend, which starts from the netlist description of the circuit and generates differential algebraic equation (DAE) based behavioral models. The physical modeling methodology in Ascend makes it possible to represent the nonlinear behavior of circuits. A modeling example is given for a better illustration of the behavioral modeling tool. Simulation results have demonstrated that both accuracy and efficiency can be achieved from the behavioral modeling tool.

Algorithms for Automatic Model Topology Formulation

A novel algorithm for automatic behavioral model topology formulation (MTF) is described in this paper. Several new terms are defined to support this formulation approach. The algorithms for determining the controllability and equivalence of branches are developed. The identification of differential pairs and current mirror structures is implemented automatically. Some other algorithms identify a subset of nodes in circuits that are extracted and modeled, while the other nodes will be collapsed. The MTF algorithm then is applied to construct a new signal-path graph, i.e., forming an equivalent circuit that has the ability to represent the behavior of the original circuit in a much-simplified form. This algorithm is implemented in a fully automated modeling tool, ASCEND, which starts from the netlist description of a circuit and generates a differential-algebraic-equation-based model. These models are able to represent static and dynamic behaviors with excellent accuracy and significant simulation speedup. The details of the MTF algorithm are described. Examples of applying the MTF algorithm for behavioral modeling are given.

Fault Current Limiter Placement Strategies and Evaluation in Two Example Systems

The growth of demand invariably lead to higher and higher fault currents, and as a consequence protection devices must have higher ratings. The integration of distributed energy resources further complicates protection schemes, especially those that assume a radial distribution scheme and power flowing in only one direction. These conditions generate an increasing demand for fault current limiters to keep fault currents within the ratings of existing protection equipment as well as to minimize the impact of distributed generation on the grid during faults. However, placement of protection equipment must be carefully considered in order to keep them cost effective and to prevent the limiters themselves from disrupting existing protective measures. This paper explores several placement and coordination guidelines, as well as provides simulations of fault current limiters placed in substations with ring bus and double bus configurations, respectively.

A methodology to coordinate solid-state fault current limiters with conventional protective devices

High short-circuit currents can cause equipment failures that conventional protective devices may not avoid. Alternatively, solid-state fault current limiters (SSFCL) are designed to limit high levels of short circuit currents, in particular, within quarter cycle. However, the SSFCL may cause sensor and protection equipment malfunction; this may lead to mis-coordination and false tripping between existing protective devices, and thus reduce system reliability. This paper addresses a methodology to coordinate conventional protective devices and a thyristor-based SSFCL in a distribution system, and analyzes potential coordination issues and effectiveness of the proposed method. It also describes an approach to produce SSFCL time-current characteristic curves (TCC) and their use in protection coordination studies. Lastly, the analysis includes SSFCL to recloser and SSFCL to fuse coordination cases and includes simulation results of several fault scenarios. Lastly, the paper describes.

Model topology formulation for nonlinear dynamic behavioral modeling

It remains difficult to generate models for analog circuits with both small and large-signal dynamic behavior. This paper describes a modeling methodology used in a new fully automated, behavioral modeling tool, ascend that starts from the netlist description of a circuit and generates differential algebraic equation (DAE) based behavioral models. These models are able to reproduce both small and large-signal dynamic behavior. The details of the model topology formulation algorithm are described, and a modeling example is given for a better illustration of the modeling procedure. The generated model contains some nonidealities of the original circuit and can be used in system validation.

A solid state fault current limiter control algorithm

The fault current limiter (FCL) is considered as the ideal solution to limit the fault current in integrated electrical power systems with distributed energy resources because of its speed of response. However, there are some practical application issues for FCL in commercial industrial deployments. In this paper, the coordination issue of FCL with the other protective devices is discussed making use of simulation and experimental results. The fundamental point of operating a FCL is that it introduces an additional equivalent impedance into the power system and thus influencing the operation of the other protective devices, sometimes, leading to malfunction. A formula is proposed in this paper to estimate the impedance range of the equivalent FCL in order to maintain the coordination with the other protective devices. An example is used to demonstrate that the fault current can be limited by controlling the switching position of a solid state fault current limiter (SSFCL) while maintaining system coordination.