Yoon Jang Chung

Correlation of the change in transfer characteristics with the interfacial trap densities of amorphous In–Ga–Zn–O thin film transistors under light illumination

The change in the transfer characteristics of amorphous In–Ga–Zn–O thin film transistors (TFTs) was investigated under light illumination at various wavelengths. The variations in the interfacial trap density (Dit) were also studied using metal-insulator-semiconductor capacitors. The transfer characteristics of the TFTs were dependent on the wavelength of illuminated light. The increase in subthreshold swing observed under light illumination of wavelengths below 550 nm (∼2.3 eV) was confirmed to be related to the increase in Dit near the conduction band edge. This Dit increase is caused by doubly ionized oxygen vacancies (VO2+) that are temporarily generated under light illumination.

Performance Variation According to Device Structure and the Source/Drain Metal Electrode of a-IGZO TFTs

The transmission-line method (TLM) was adopted to clarify the causes of device performance variation according to the source/drain metal electrode and device structure of a thin-film transistor using an amorphous indium-gallium-zinc-oxide channel. Using the TLM, the channel characteristics independent of contact resistance were extracted for the two different contact metals, i.e., Ti and Mo. Based on these results, the mobility characteristics were compared in terms of device scaling and contact structure in the source/drain overlap region. In addition, the transport characteristics according to the contact structure of the source/drain metal electrode were investigated in detail and reproduced using the simulation model.

Vertically integrated submicron amorphous-In2Ga2ZnO7 thin film transistor using a low temperature process

In this work, vertically integrated amorphous-In2Ga2ZnO7 (a-IGZO) thin film transistors (V-TFTs) with 310 nm channel length were fabricated using a low temperature process (<300  °C), and their device performance was evaluated. The fabricated V-TFTs show well behaved transfer characteristics with an Ion/Ioff current ratio greater than 104 and a threshold voltage of 1.7 V. The influence of the vertical structure on device performance was analyzed in detail. In addition, current polarity characteristics that arise from different metal/a-IGZO contacts were also examined. The non-optimum performance of the V-TFTs was attributed to the fringing-field effect, high defect density, and large source/drain contact resistance.

A simple method for cleaning graphene surfaces with an electrostatic force.

DOI: 10.1002/adma.201303199 Graphene is a 2D conductive nanomaterial composed of a honeycomb-structured array of carbon atoms. [ 1,2 ] It is useful in a variety of fi elds due to its structural and chemical stability and because it possesses unprecedented optical and electrical properties. [ 3–7 ] Graphene can be produced by both bottom-up (chemical vapor deposition: CVD) [ 8–11 ] and top-down (chemical or mechanical exfoliation) approaches. [ 2,12–14 ] CVD techniques can yield layer-controlled graphene sheets over large areas using Ni or Cu catalyst substrates; however, the CVD process is limited to very specifi c growth templates, and graphene is seldom directly grown on insulating substrates. Graphene grown on Cu or Ni catalyst fi lms must be transferred to a target substrate for use in applications. The procedures involved in transferring these fi lms always involve a supporting polymer contact layer because the mechanical strength of the one-atom-thick graphene is insuffi cient to handle the transfer processes. The most commonly used supporting layer materials are poly(methyl methacrylate) (PMMA), polycarbonates (PCs), or conventional photoresistive (PR) layers. [ 8–11,15–19 ] After the transfer step, the supporting layer materials must be removed from the graphene surface. The chemical stripping processes involved in removing the supporting layer are routine because most supporting layer materials readily dissolve in common solvents, such as acetone; however, PMMA layers in direct contact with a graphene layer (1–5 nm from the surface) leave “PMMA-G” contamination materials that cannot be removed using simple chemical means. [ 20–22 ] The residual PMMA-G not only degrades and changes the electrical characteristics of the graphene layer, but it also introduces uncertainty into studies of the intrinsic surface properties of graphene, the development of sensor devices, the fabrication of cell culture substrates for accelerating stem cell differentiation, and the fabrication of atomic-scale honeycomb templates. [ 23–25 ] Many attempts have been made to resolve these issues, and annealing methods, such as H 2 /Ar annealing, [ 20 ] vacuum annealing, [ 21 ] and Joule heating, [ 26 ] have proven to be successful. Some approaches have “scraped the surfaces clean? using atomic force microscopy (AFM) tips. [ 27 ] Hightemperature annealing processes (>250 °C) can introduce defects into graphene surfaces, and process temperatures can be much too high for use with fl exible substrate-based devices. High-temperature annealing normally requires vacuum facilities and/or the application of electrical energy, which increases production costs. Although AFM-derived mechanical cleaning methods avoid some of these complications, their use is limited to laboratory-scale because the methods are extremely lowthroughput. Therefore, an effective cleaning method that does not involve high-temperature heat treatments would greatly benefi t practical applications that rely on transferred graphene. Traditional surface cleaning methods involve rubbing a piece of cloth over the surface. Empirical evidence from everyday life clearly shows that a combination of mechanical abrasion and detergent is much more effective toward cleaning than the simple use of detergents only; however, abrasion methods cannot be used on materials that are mechanically weak. Nanostructured materials, such as graphene or carbon nanotubes, generally have a much larger mechanical strength than conventional steel of the same dimensions; however, the aggregate strength of nanostructured materials is usually not suffi ciently large to withstand macroscopic mechanical stresses. Mechanical abrasion is generally not used to clean the surfaces of nanoscale materials. Electrostatic interactions can remove charged impurities and, therefore, present an alternative approach to direct mechanical cleaning. Rubbing a balloon or a piece of plastic on ones head to induce ones hair to rise is a familiar childhood demonstration of electrostatic interactions, in which stationary or slow-moving electric charges build up in a material. As two interfaces are rubbed against one another, electrons can cross the interface of the materials and generate a charge disparity in each of the materials. The direction of electron transfer depends on the ability of the material to accept a negative charge. For example, as a piece of rubber is rubbed against a cloth, electrons are transferred from the cloth to the rubber. The rubber becomes negatively charged and the cloth becomes positively charged. Because the presence of a static charge creates a non-uniform electrostatic fi eld that tends to attract matter toward it, a material with a large amount of static charge can be used to remove dust from a surface. In this study, extremely fi ne cloth fi bers were used to apply electrostatic-force cleaning (EFC) to a graphene surface by removing the residual PMMA-G layers, yielding an intrinsic graphene surface without causing damage to the structural integrity. The process of removing the PMMA-G layer was monitored on a step-by-step basis using optical microscopy

The effects of device geometry on the negative bias temperature instability of Hf-In-Zn-O thin film transistors under light illumination

The negative bias illumination temperature stress instability of amorphous Hf-In-Zn-O thin film transistors with different dimensions was evaluated. The threshold voltage (Vth) shift increased in devices with shorter channel lengths but showed almost no association with the channel width. This behavior was attributed to the diffusion and drift of the photogenerated holes at the channel/dielectric interface from regions near the drain to those near the source, which were due to the simultaneous presence of gate and drain biases. The Vth near the source, which shows the largest shift and hence has the highest local value, governs the overall Vth.

Indium tin oxide/InGaZnO bilayer stacks for enhanced mobility and optical stability in amorphous oxide thin film transistors

Optically more stable, high mobility InGaZnO thin film transistors were fabricated by implementing ultrathin In2O3-SnO2 (ITO) layers at the gate dielectric/semiconductor interface. The optimized device portrayed a high saturation mobility of ∼80 cm2/V s with off current values lower than 10−11A. The ITO layer also acted as a hole filter layer, and hole current and threshold voltage shift values measured under negative bias illumination conditions showed that a significant amount of photo-generated charge carriers were annihilated before reaching the gate insulator. This effect was more evident at larger intensities, showing threshold voltage shift values reduced by more than ∼70% under stress conditions.

The charge trapping characteristics of Si3N4 and Al2O3 layers on amorphous-indium-gallium-zinc oxide thin films for memory application

The charge trapping characteristics of 30-nm-thick Si3N4 and 3-nm-thick Al2O3 layers between amorphous In-Ga-Zn-O thin films and 100-nm-thick blocking oxides made of thermal SiO2 were examined. The Si3N4 layer showed several discrete trap levels with relatively low density, while the Al2O3 layer showed a higher trap density with continuous distribution for electron trapping. When no tunneling oxide was adopted, the trapped carriers were easily detrapped, even at room temperature. Adoption of a 6-nm-thick SiO2 tunneling layer grown by atomic layer deposition largely improved the retention of the trapped charges and retained ∼60% of the trapped charges even after 10 000 s.

A study on the influence of local doping in atomic layer deposited Al:ZnO thin film transistors

Local doping of Al:ZnO into a ZnO matrix was performed vertically at various positions in a thin film using atomic layer deposition, and its influence was investigated by analyzing thin film transistor (TFT) characteristics. The position specific dopant distribution in the films was confirmed by high resolution transmission electron microscopy. It was found that doping specific locations in the active channel layer of a TFT had a different impact on its electrical characteristics. When near the semiconductor/gate dielectric interface, doping had a significant impact on the mobility of the TFT devices, which showed a gradual recovery as the doped region was moved away from the interface. The original characteristics of the device were almost completely restored once the doped region was moved more than 15 nm away from the interface, and when moved further away the output characteristics portrayed a shift in threshold voltage while preserving all other electrical characteristics. Various doping concentrations were implemented in regions both near and far away from the interface to gain a better understanding of the phenomena. The experimental results given here imply that the geographical position of doping is as important as selecting a dopant material in the device optimization of TFTs.

The Electrical Properties of Asymmetric Schottky Contact Thin-Film Transistors with Amorphous-

Asymmetric Schottky contact thin-film-transistors (ASC-TFTs) with an amorphous- In2Ga2ZnO7 channel were fabricated, and their operation characteristics were examined. Ti, Ni, and Pt were evaluated as source/drain metal, and the variations in the device performance were analyzed in terms of energy level and bias polarity, which were carefully simulated to understand the influence of the contact properties on the device performance. The contact nature largely influenced the distribution of potential under the given gate and drain biases, as well as the accompanying carrier accumulation layer and current path formation. Schottky-type contact induced conduction path formation even on the back surface of the channel when drain voltage was high even with sufficiently high gate bias being applied. Based on these results, by applying different metal for each source and drain metal, ASC-TFTs integrating TFTs and Schottky diodes were fabricated, which showed a rectification ratio of drain current higher than 108 according to the bias direction. In addition, the transfer and output characteristics of ASC-TFTs were evaluated for various operation regimes, and the roles of the Schottky junction in device operation were studied in detail.

\hbox{In}_{2}\hbox{Ga}_{2}\hbox{ZnO}_{7}

A simple optical model based on the transfer matrix method was used to simulate photon absorption in oxide semiconductor systems with varying insulator thickness in the thin film transistor (TFT) structure. For comparison with actual experimental results, hole current was measured in transparent metal/semiconductor/insulator/metal capacitor stacks under light illumination, and the threshold voltage shift under negative bias illumination stress conditions was also measured in the TFT structure. In each structure, experimental data showed variance as the insulator thickness changed, and these results agreed well with the simulations. The results showed that light interference in multi‐layered devices has a crucial influence on the reliability of them under illumination and that they should be considered when designing systems that work under these conditions. The accuracy of the simulations suggests they can be implemented to minimize instability issues in oxide TFTs for display.