Jung-Hae Choi

Vertically integrated submicron amorphous-In2Ga2ZnO7 thin film transistor using a low temperature process

In this work, vertically integrated amorphous-In2Ga2ZnO7 (a-IGZO) thin film transistors (V-TFTs) with 310 nm channel length were fabricated using a low temperature process (<300  °C), and their device performance was evaluated. The fabricated V-TFTs show well behaved transfer characteristics with an Ion/Ioff current ratio greater than 104 and a threshold voltage of 1.7 V. The influence of the vertical structure on device performance was analyzed in detail. In addition, current polarity characteristics that arise from different metal/a-IGZO contacts were also examined. The non-optimum performance of the V-TFTs was attributed to the fringing-field effect, high defect density, and large source/drain contact resistance.

Theoretical and experimental studies on the electronic structure of crystalline and amorphous ZnSnO3 thin films

The influence of structural disorder on the electronic structure of amorphous ZnSnO3 was examined by ab-initio calculations. The calculation results are compared with the experimental results using as-deposited and annealed ZnSnO3 films grown by atomic layer deposition. The O K-edge X-ray absorption spectroscopy, X-ray diffraction, and thin-film transistors were employed in the experiment. The conduction band minima of amorphous and crystalline ZnSnO3 mainly consisted of Sn 5s state, while a higher non-uniform localization of these states was observed in the amorphous phase compared with the crystalline counterpart. The experimental results coincide well with the theoretical results.

In situ fabrication of single-crystal Fe nanomagnet arrays

We produced single-crystalline Fe nanodot arrays grown in situ on a W(110) substrate in an ultrahigh vacuum system. An alumina shadow mask with perfectly ordered holes was used for Fe deposition. Polycrystalline Fe nanodots could be crystallized to single-domain nanodots by thermal annealing. After annealing, Fe wets tungsten substrate with one monolayer, but Fe islands neither coalesce nor form an alloy with the substrate.

The charge trapping characteristics of Si3N4 and Al2O3 layers on amorphous-indium-gallium-zinc oxide thin films for memory application

The charge trapping characteristics of 30-nm-thick Si3N4 and 3-nm-thick Al2O3 layers between amorphous In-Ga-Zn-O thin films and 100-nm-thick blocking oxides made of thermal SiO2 were examined. The Si3N4 layer showed several discrete trap levels with relatively low density, while the Al2O3 layer showed a higher trap density with continuous distribution for electron trapping. When no tunneling oxide was adopted, the trapped carriers were easily detrapped, even at room temperature. Adoption of a 6-nm-thick SiO2 tunneling layer grown by atomic layer deposition largely improved the retention of the trapped charges and retained ∼60% of the trapped charges even after 10 000 s.

Growth, Quantitative Growth Analysis, and Applications of Graphene on γ-Al2O3 catalysts

The possibilities offered by catalytic γ-Al2O3 substrates are explored, and the mechanism governing graphene formation thereon is elucidated using both numerical simulations and experiments. The growth scheme offers metal-free synthesis at low temperature, grain-size customization, large-area uniformity of electrical properties, single-step preparation of graphene/dielectric structures, and readily detachable graphene. We quantify based on thermodynamic principles the activation energies associated with graphene nucleation/growth on γ-Al2O3, verifying the low physical and chemical barriers. Importantly, we derive a universal equation governing the adsorption-based synthesis of graphene over a wide range of temperatures in both catalytic and spontaneous growth regimes. Experimental results support the equation, highlighting the catalytic function of γ-Al2O3 at low temperatures. The synthesized graphene is manually incorporated as a ‘graphene sticker’ into an ultrafast mode-locked laser.

Silicon-based field-effect-transistor cantilever for surface potential mapping

A silicon-based scanning probe with a field effect transistor (FET) has been developed. The FET is integrated onto an atomic force microscope cantilever with a sharpened tip. The commonly used complementary-metal–oxide–semiconductor process has been employed to construct the FET using a silicon-on-insulator wafer. The probe is used to measure a surface potential with a resolution of <300 nm when determined by the edge of patterned SiO2 islands. The probe can be also used to detect local properties on semiconductor surfaces, such as isolated charge distributions on a surface or at subsurface.

Alternative interpretations for decreasing voltage with increasing charge in ferroelectric capacitors

Recent claim on the direct observation of a negative capacitance (NC) effect from a single layer epitaxial Pb(Zr0.2,Ti0.8)O3 (PZT) thin film was carefully reexamined, and alternative interpretations that can explain the experimental results without invoking the NC effect are provided. Any actual ferroelectric capacitor has an interfacial layer, and experiment always measures the sum of voltages across the interface layer and the ferroelectric layer. The main observation of decreasing ferroelectric capacitor voltage (VF) for increasing ferroelectric capacitor charge (QF), claimed to be the direct evidence for the NC effect, could be alternatively interpreted by either the sudden increase in the positive capacitance of a ferroelectric capacitor or decrease in the voltage across the interfacial layer due to resistance degradation. The experimental time-transient VF and QF could be precisely simulated by these alternative models that fundamentally assumes the reverse domain nucleation and growth. Supplementary experiments using an epitaxial BaTiO3 film supported this claim. This, however, does not necessarily mean that the realization of the NC effect within the ferroelectric layer is impractical under appropriate conditions. Rather, the circuit suggested by Khan et al. may not be useful to observe the NC effect directly.

Resistance switching behavior of atomic layer deposited SrTiO3 film through possible formation of Sr2Ti6O13 or Sr1Ti11O20 phases.

Identification of microstructural evolution of nanoscale conducting phase, such as conducting filament (CF), in many resistance switching (RS) devices is a crucial factor to unambiguously understand the electrical behaviours of the RS-based electronic devices. Among the diverse RS material systems, oxide-based redox system comprises the major category of these intriguing electronic devices, where the local, along both lateral and vertical directions of thin films, changes in oxygen chemistry has been suggested to be the main RS mechanism. However, there are systems which involve distinctive crystallographic phases as CF; the Magnéli phase in TiO2 is one of the very well-known examples. The current research reports the possible presence of distinctive local conducting phase in atomic layer deposited SrTiO3 RS thin film. The conducting phase was identified through extensive transmission electron microscopy studies, which indicated that oxygen-deficient Sr2Ti6O13 or Sr1Ti11O20 phase was presumably present mainly along the grain boundaries of SrTiO3 after the unipolar set switching in Pt/TiN/SrTiO3/Pt structure. A detailed electrical characterization revealed that the samples showed typical bipolar and complementary RS after the memory cell was unipolar reset.

Strain evolution of each type of grains in poly-crystalline (Ba,Sr)TiO 3 thin films grown by sputtering

The strain states of [111]-, [110]-, and [002]-oriented grains in poly-crystalline sputtered (Ba,Sr)TiO3 thin films on highly [111]-oriented Pt electrode/Si substrates were carefully examined by X-ray diffraction techniques. Remarkably, [002]-oriented grains respond more while [110]- and [111]-oriented grains do less than the theoretically estimated responses, which is understandable from the arrangement of the TiO6 octahedra with respect to the stress direction. Furthermore, such mechanical responses are completely independent of the degree of crystallization and film thickness. The transition growth temperature between the positive and negative strains was also different depending on the grain orientation. The unstrained lattice parameter for each type of grain was different suggesting that the oxygen vacancy concentration for each type of grain is different, too. The results reveal that polycrystalline (Ba,Sr)TiO3 thin films are not an aggregation of differently oriented grains which simply follow the mechanical behavior of single crystal with different orientations.

Double-layered vertically integrated amorphous-In2Ga2ZnO7 thin-film transistor

Two serially connected and vertically integrated amorphous-In2Ga2ZnO7 thin film transistors (V-TFTs) with ∼600 and 400-nm channel lengths were fabricated. Top and bottom V-TFTs showed well-behaved transfer characteristics with an Ion/Ioff ratio of ∼108 and a sub-threshold swing of ∼0.6 V/dec., which are much improved results compared with the previous report on single-layer V-TFTs. Electrical performances of two V-TFTs were cross-checked, and they showed certain influences from the other device depending on operation conditions, which was attributed to charge trapping in the gate dielectric layer during gate voltage sweeping. V-TFT with thermally grown SiO2 showed negligible charge trapping behavior.