Yoon-Woo Lee

A 0.18 /spl mu/m CMOS SoC of a front-end hardware platform for DVD-multi recorders

This work presents a 0.18 /spl mu/m CMOS system on a chip (SoC) that is a hardware platform for the front-end of DVD-multi recorders (FESOC). It has one 32 bit RISC CPU and one 16 bit DSP as well as most of the necessary components for DVD recorders, except for an analog front end (AFE) and some memories. The necessary building blocks are a partial response channel maximum likelihood detector (PRML), a servo signal processor (SERVO), write strategy controller (WSC), a data processor (DP), an AT-attachment packet interface (ATAPI), and a micro computer unit (MCU). Using a three-layered bus architecture enables this FESOC to work well with a 16 bit-wide bus at 67 MHz for 8/spl times/ DVD operation, and to be implemented with a short development time. The FESOC is fabricated in 0.18 /spl mu/m 1-poly 5-metal CMOS technology. It contains 8.4 million transistors in a 46 mm/sup 2/ die and consumes 1.4 W with a channel clock of 209.28 MHz in 8/spl times/ operation mode.

Block and Codeword Interleaving Scheme for the High Density Digital Versatile Disc

The effect of noises from smaller dusts and scratches is higher than the conventional optical storage systems, e.g., compact disc(CD) or digital versatile disc(DVD) by the higher numerical aperture (NA=0.85) and thin cover layer (0.1 mm) of the high density DVD. Accordingly, new error correcting code (ECC) is needed to correct not only both short burst errors and random errors but also long burst errors. So, the interleaving scheme between two ECC blocks is considered to improve the error correction capability. In this paper, we will show our new block and codeword interleaving scheme (BCIS) and calculate the block error rate of BCIS after error correcting by probability method under the error model of Sonys burst error distribution and compare with the conventional reed-solomon product code(RSPC) of DVD.