Yosef Y. Shacham-Diamand

Electroless Cu and barrier layers for subhalf-micron multilevel interconnects

Characteristics of electroless Cu, Co and Ni alloys for a multilevel metallization as well as for local interconnects and silicide formations for sub-0.5 micrometers ULSIs are presented. An integration of the electroless Cu and CoWP multilayers in an ULSI damascene process for the quarter-micron Cu interconnects of aspect ratio 4:1 is discussed. The following techniques are involved in this process: conformal electroless deposition of CoWP barrier on the thin sputtered Co seed layer, electroless Cu deposition directly onto CoWP barrier to fill a deep trench or a via, removal of the excess barrier and Cu on the oxide by chemical mechanical polishing, Pd activation of the Cu surface and selective electroless CoWP deposition onto Pd- activated in-laid Cu lines to prevent Cu oxidation and corrosion. The study of the selective electroless NiP deposition on Si for silicide formations for sub-0.25micrometers ULSI technology is also presented.

Electroless CoWP Barrier/Protection Layer Deposition for Cu Metallization

A fully encapsulated copper interconnect with CoWP barrier and protection layer can be produced by conformai electroless CoWP barrier layer deposition at the bottom and on the sidewalls of trenches and selective electroless CoWP deposition on in-laid Cu lines. The electroless CoWP deposition is an autocatalytic reaction with activation energy of about 0.985 eV. Deposition rate of about 10 nm/min at 80°C and average surface roughness of 5 nm for 200 nm thick films were measured. CoWP layer with resistivity of 25 μOhms·cm was obtained. Resistivity of electroless CoWP films was decreased from 25 μOhms·cm to 20 μOhms·cm after annealing in vacuum with 10 −7 torr at 400°C for 30 min. The RBS spectra of the Cu/CoWP/Co/Si structure formed by electroless CoWP barrier and Cu deposition and annealed at 400°C for 60 min in vacuum 10 −7 torr showed no interdiffusion in deposited films.

Semi-analytical model for charge control in SiGe quantum well MOS structures

Abstract This paper discusses a semi-analytical model to calculate charge distribution in a silicon Metal-Oxide-Semiconductor (MOS) structure with a buried, strained Si 1−x Ge x quantum well. This charge distribution model is applicable to a device structure that consists of the following layer sequence: n -type substrate; p + doping spike; Si spacer layer; SiGe quantum well; Si cap layer; insulator and gate. The sheet density of mobile charge in the SiGe well is calculated using a quantum mechanical potential well description with the addition of a first-order perturbation analysis to accommodate the application of a gate bias. The carrier density in the inversion layer at the oxide/Si interface is found in a similar manner using the triangular well approximation. These expressions are coupled with an explicit algorithm to compute the electrostatic potential and depletion charge for various gate biases. Case studies are presented for quantum well MOS structures reported in the literature, and the carrier distributions found utilizing the semi-analytical model are in reasonable agreement with those calculated numerically via self-consistent solution of Schroedingers and Poissons equations. This semi-analytical framework allows a means to relate the effects of changing device physical parameters on circuit oriented characteristics. With an appropriate carrier transport description, this one-dimensional treatment can be expanded to quantum well MOS-Field Effect Transistors (MOSFETs) to quantify their static and dynamic characteristics.

p-channel MIS double-metal process InSb monolithic unit cell for infrared imaging

A new approach to the fabrication of monolithic infrared focal plane arrays is presented and examined in this paper. The array is based on photovoltaic diodes, parallel integration capacitors, and MIS field effect transistors (FET). The photodiode is connected directly to the integrating capacitor while the MISFET serves as a pass gate to the video line. This configuration is operated in the pseudo-staring mode. The array was implemented in InSb, in a process based on a new passivation in which a photo chemical oxidation of InSb is followed by a conventional photo chemical SiO2 growth. A two-level metallization process was developed serving both for electrical connection and optical coverage. Two configurations were tested for the layout of the two metal layers. In addition, the lower metallization was implemented in Cr, Ti, and Al. The optimal structure is a planar array with Cr as the first metal layer which forms the source and drain contacts.

A new single-layer plasma-developable photoresist using the catalysed crosslinking of poly(4-hydroxystyrene)via photogenerated acid

A new single-layer, dry developable chemically amplified resist is described. The resist consists of poly(4-hydroxystyrene), 1,2,4,5-tetra(acetoxymethyl)benzene and triphenylsulfonium hexafluoroantimonate, and functions via crosslinking as a result of an acid-catalysed electrophilic aromatic substitution reaction. In contrast to the normal wet resist development process that leads to a negative-tone image, a gas-phase modification of the exposed polymer film, followed by reactive oxygen etching, leads to a positive-tone image. The post-exposure modification is accomplished using gaseous 1,1,1,3,3,3-hexamethyldisilazane, a reagent that is able to diffuse selectively into the non-exposed, non-crosslinked regions of the polymer film to react with the poly(4-hydroxystyrene) and form silyl ethers. Dry-development of the treated film in an O2 plasma removes those areas of the film that have remained unsilylated, producing a positive-tone relief image.

Process optimization of 200 nm wide trenches in SiO2 using a chemically amplified acid catalyzed e‐beam resist

In this article we present a novel acid catalyzed chemically amplified resist and the associated silicon‐dioxide etch process that was developed using that resist. The 200 nm wide and 250 nm deep trenches in the silicon dioxide are part of a multilevel fully planar metallization scheme, where copper lines are fully imbedded in the interlevel dielectric. Conventional resist materials are not sensitive enough to be used in high‐throughput production and in many cases their selectivity versus silicon dioxide reactive ion etching is low. Resist materials based on acid catalyzed chemical amplification show very desirable properties with respect to their sensitivity, flexibility in design, and resolution capability. The resolution capability extends down to 200 nm for 290 nm thick resist presented in this report. Moreover, as such resists meet the requirements of deep UV, x‐ray, and e‐beam exposure tools, it is expected that they will replace the ‘‘standard’’ novolac resists in many applications. A process wind...

Characterization of spin-on titanium nitride

The properties of spin-on titanium-nitride (SO-TiN) thin films were optimized for integrated- circuit application. The two steps of the spin-on process were characterized: one, the initial step in which a thin-film titanium oxide is formed, and two, the conversion of the thin film to titanium-nitride (TiN) by rapid thermal processing in ammonia. The spin-on TiN showed a uniform coating on a flat wafer surface for all the precursors. However, on non-planar topography some solutions produced cracked films while others did not. The precursors effect was investigated, and it is proposed that the optimized precursor should include more carbon in the initial annealing stage so the film does not crack. The chosen precursor, titanium- tertiary-butoxide, was investigated and characterized versus processing temperature, heating rate, and gas flow. The experiment was designed at the 700 degree(s)C - 1000 degree(s)C temperature range, with 0.1 - 200 degree(s)C/sec. heating rate, and hold time of 30 - 300 sec. at the upper temperature before rapid cool down. The optimal processing conditions at NH3 are heating at 100 - 120 degree(s)C/sec. ramp from room temperature up to 900 degree(s)C - 1000 degree(s)C where the wafer is annealed for 30 - 100 seconds before rapid cool down to room temperature.

Dry lithography of chemically amplified acid-catalyzed deep-UV and e-beam resist

The process, chemistry, and characterization of the silylation and dry-development of acid catalyzed resist is described. The resist is sensitive to deep-UV, x ray, and e-beam exposure and its sensitivity can be tailored by the relative concentration of its components. The resist is positive or negative for dry or wet development, respectively. Two silylation agents were studied: Hexamethyldisilazane (HMDS) and N,N-Dimethylaminotrimethylsilane (DMATMS). The silylation was characterized by Fourier-transform-infrared (FTIR) transmission spectroscopy and Rutherford-backscattering spectrometry (RBS). FTIR revealed the total number of OH and SiO bonds, while RBS revealed the composition profile in various regions of the resist. The silylation by HMDS was not well controlled and was characterized by a large incubation period followed by fast penetration. The DMATMS silylation process, however, was well controlled and reproducible. The penetration of the silicon atoms monotonically increased with time until it reached saturation. Films patterned by deep-UV (254 nm) exposure were silylated with DMATMS and were etched by an oxygen plasma in a magnetron ion etcher (MIE). The etch rate of the oxygen plasma was characterized for the unexposed, silylated regions, as well as for the exposed, unsilylated regions. The optimized dry-development process is described and SEM cross sections of lines as narrow as 0.4 micrometers wide are presented.

Monolithic focal-plane cell in InSb

A monolithic infrared focal plane array where photo-diodes and field effect transistors are integrated is presented. The photodiode is connected directly to the integrating capacitor while the transistor controls the integrated signal-charge transfer to the video line. The operating modes of such array are discussed and especially the pseudo-staring mode. Such arrays were produced and their system performance were investigated. The detectors average specific detectivity D*(lambda )(f/no equals 1, (lambda) equals 3.83 micrometers ) was equal to 1.3 X 1011 [cm-Hz1/2/W] and was used to calculate the Noise Equivalent Temperature Difference (NETD) as a function of the number of detectors and vectors. The NETD was estimated to be of 0.039 K for an optimal 5 vectors array.

Narrow (0.1 um to 0.5 um) copper lines for ultra-large-scale integration technology

Copper has been studied for Ultra-Large-Scale-Integration (ULSI) interconnect technology. A copper metalization system is proposed which includes both conducting and insulating barrier metals. Copper lines with minimum dimension of 100 nm were fabricated by electroless copper deposition. An alkaline-free deposition solution has been studied in addition to the conventional NaOH based solution. Two techniques have been developed to produce copper nanolines. The first method produced smooth non-planar copper lines with vertical sidewalls. Aspect ratios (height/width) as high as 3:1 have been obtained. The second fabrication technique formed a planar topography in which the copper is fully buried in an interlevel dielectric. Copper lines fabricated by both methods have been characterized by SEM. Problems unique to selective copper deposition are presented and discussed.