Valery Dubin

Copper electroless deposition technology for ultra-large-scale-integration (ULSI) metallization

Abstract In this paper we present the technology of electroless Cu deposition for ultra-large-scale integration. The technology has several components: the solution chemistry, the operation conditions, the seeding, the equipment and the process integration. Sodium-free solution was used and optimized to achieve a deposition rate in the range of 75–120 nm/min, resistivity ϱ less than 2 cm, with a uniformity better than 3% on 6″ wafers and 5% on 8″ wafers. The surface roughness of the films was in the range of 10–15 nm for a 1.5 μm thick layer. The highly uniform deposition is achieved by using a novel sacrificial aluminium protected copper seeding. This method protects the catalytic properties of the Cu, which is exposed to the solution after the aluminium dissolution. Another seeding method has been developed with Cu contact displacement deposition on a TiN layer using a solution that contains copper and fluorine ions. Several electroless Cu deposition processes have been developed in both blanket and selective deposition modes, using Al protected Cu seed and contact displacement seeding. The technology was capable of obtaining 0.3 μm electroless Cu-filled trenches and vias with an aspect ratio as high as 5:1. The process topography is modelled numerically for vias, trenches, and micro-tunnels with high aspect ratio (up to 400:1). The copper diffusivity was found to be in the range of 10 −5 cm 2 /sec at 40°C and it was used in the 2-D modelling of copper deposition in via contacts and trenches.

Electrochemical aspects of new materials and technologies in microelectronics

Major scaling issues, which need to be addressed to continue scaling according to Moores law, include increase of transistor leakage due to use of thin gate oxide (about 1 nm limit for SiO2), power (reaching 100 W/cm2) and RC delay (dielectric constant limit is 1 for air and Cu resistivity increases with scaling down the feature sizes). Integration of new materials and technologies will allow us to continue scaling and improve device performance. Examples of new materials include high-k dielectrics and strained silicon in the frond end of wafer processing, low-k carbon-doped oxide and electroplated copper in the back end of wafer processing as well as electroplated bumps, high thermal conductivity interface, heat sink and heat spreader materials in packaging. Electrochemical technologies will play an increasingly important role in silicon technology due to low cost, use of self-assembly processing and self-aligned growth ability. New electrochemical technologies in silicon processing include copper electroplating (replaced Al interconnect to reduce RC delay and increase reliability), bump electroplating (replaced wire bonding to allow increased I/O and improve reliability), and porous silicon for silicon on isolator fabrication (to reduce transistor leakage). Copper electroplating allows a low R, an excellent gap fill capability and superior materials properties with (111) textured Cu films and large grain size, and a stable and controlled process.

Electroless Cu and barrier layers for subhalf-micron multilevel interconnects

Characteristics of electroless Cu, Co and Ni alloys for a multilevel metallization as well as for local interconnects and silicide formations for sub-0.5 micrometers ULSIs are presented. An integration of the electroless Cu and CoWP multilayers in an ULSI damascene process for the quarter-micron Cu interconnects of aspect ratio 4:1 is discussed. The following techniques are involved in this process: conformal electroless deposition of CoWP barrier on the thin sputtered Co seed layer, electroless Cu deposition directly onto CoWP barrier to fill a deep trench or a via, removal of the excess barrier and Cu on the oxide by chemical mechanical polishing, Pd activation of the Cu surface and selective electroless CoWP deposition onto Pd- activated in-laid Cu lines to prevent Cu oxidation and corrosion. The study of the selective electroless NiP deposition on Si for silicide formations for sub-0.25micrometers ULSI technology is also presented.

Sub-Half Micron Electroless Cu Metallization

Electroless Cu metallization has been fabricated by blanket electroless Cu deposition into the trenches in SiO 2 dilectric layer on sputtered Cu seed layer with Ta diffusion layer and Al protection layer. Chemical-mechanical polishing of copper has been used to planarize the structure. Selective electroless CoWP layer has been deposited to protect inlaid Cu metallization.

Microstructure And Mechanical Properties Of Electroplated Cu Films For Damascene Ulsi Metallization

Copper has been deposited for filling sub-0.5 μm trenches by using electroplating. Electroplating with pulse plating conditions provides the high deposition rate (0.5–1 μm/min) and defect-free filling the 0.25 μm trenches and vias of high aspect ratio (>4:1). Enhanced copper electroplating at the trench bottom has been achieved. The median grain size of electroplated copper was measured to be about 1 jim and the lognormal standard deviation is about 0.4 μm. Strong texture was observed in electroplated Cu film. Low stress of electroplated Cu films and excellent adhesion of plated Cu to sputtered Cu seed were observed.

Electroless CoWP Barrier/Protection Layer Deposition for Cu Metallization

A fully encapsulated copper interconnect with CoWP barrier and protection layer can be produced by conformai electroless CoWP barrier layer deposition at the bottom and on the sidewalls of trenches and selective electroless CoWP deposition on in-laid Cu lines. The electroless CoWP deposition is an autocatalytic reaction with activation energy of about 0.985 eV. Deposition rate of about 10 nm/min at 80°C and average surface roughness of 5 nm for 200 nm thick films were measured. CoWP layer with resistivity of 25 μOhms·cm was obtained. Resistivity of electroless CoWP films was decreased from 25 μOhms·cm to 20 μOhms·cm after annealing in vacuum with 10 −7 torr at 400°C for 30 min. The RBS spectra of the Cu/CoWP/Co/Si structure formed by electroless CoWP barrier and Cu deposition and annealed at 400°C for 60 min in vacuum 10 −7 torr showed no interdiffusion in deposited films.