Yoshiaki Koga

A proposal for error-tolerating codes

An extended concept of error-tolerating codes is presented and some examples of error-tolerating codes are introduced. An erroneous codeword of the proposed error-tolerating code may occur in the codespace; however, in this case, the erroneous codeword is required to be in a defined neighborhood of the original codeword. When no error is detected in a word, the word may differ from the original codeword, but it is trustworthy and can be used in a system without any error-correction or error-recovery procedures. An error-tolerating code is presented as an example. This code can be used for to implement analog-to-digital converting devices which are useful for dependable high-speed real-time control systems.

A proposal of fault-checking fuzzy control

The effects of faults in fuzzy control systems are examined and are shown not to be negligible. A fault-detecting method that increases the fault tolerance characteristics of fuzzy control systems is proposed. Simulation results show the validity of the proposed fault-checking method for all kinds of faults considered.<<ETX>>

Implementation and evaluation for dependable bus control using CPLD

Bus systems are used in computers as essential architecture, and dependability of bus systems should be accomplished reasonably for various applications. In this paper, we will present dependable bus operations with actual implementation and evaluation by CPLD. Most of the bus systems control transition of some classified phases with synchronous clock or guard time to avoid incorrect phase transition. However, these phase control methods may degrade system performance or cause incorrect operations. We design an asynchronous sequential circuit for bus phase control without clock or guard time. This circuit prevents incorrect phase transition at the time when large input delay or erroneous input occurs. We estimate probability of incorrect phase transition with single stuck-at fault on input signals. From the result of estimation, we also design checking system verifying outputs of initiator and target devices. Incorrect phase transition with single stuck-at fault occurred between both sequential circuits is inhibited completely by implementation of the system.

Fault tolerant multi-processor communication systems using bank memory switching

The paper proposes a new fault tolerant communication scheme for real-time operations and three new interconnection networks to construct a fault tolerant multi-processor system for pipeline processings. The proposed communication scheme using bank memory switching technique has an advantage to make a fault tolerant pipeline system so that it can detect any failure caused in a processing element of the system. In addition, it can overcome conventional problems caused in interconnection circuits to data flow with one direction such as a pipeline processing.<<ETX>>

Fault tolerant IC chip for crystal oscillators

Some applications of multiprocessor systems require the system to synchronize their clocks with each other. There are many studies on fault-tolerant clock synchronization methods. However. algorithms proposed in previous work cannot achieve both tight synchronization and cost-effectiveness. To solve these two problems, the authors have proposed a construction method for a highly reliable clock generator. It can achieve tight synchronization of clocks using a coupling device such as a crystal or a capacitor. An IC implementation of the highly reliable clock generator which is useful for real applications such as off-the-shelf components, and its evaluation are presented.<<ETX>>

Technologies for designing dependable A/D converters

Although considerable research has been conducted on fault tolerance at the system level and results in system level fault tolerance have been applied to some actual systems, only a few research reports on fault tolerant A/D converters have appeared in the literature. Since A/D converters are extensively used in many actual systems and have important roles as input devices for digital processing in real time systems, it is important to develop technologies for designing dependable A/D converters. We review the technologies for the design of dependable A/D converters, including some of the patents in this area and the results of our research.

Realization of a self-testing bus arbiter

This paper discusses a realization of a self-testing distributed arbiter for bus-connected systems. One of the traditional schemes for arbitration is that each of the connected modules acknowledges when the arbitration is completed. However, there is a problem in that a dedicated software as well as a complex hardware are required, which increases the cost and affects the through-put of the system. The method proposed in this paper assigns a certain code as the module number for verification of arbitration, and detects failure by a retrial using its complement. In other words, the method aims at secure arbitration using time-space redundancy, i.e., redundancy in time and redundancy in code space, and at realization by as simple a circuit as possible, with the self-testing function. It is verified from the results of simulation that all single stuck-at faults can be detected for the case of 3 bits, under the assumption that all possible inputs are given before the next failure is produced. Even if not all of the inputs are given, there was no observed extraordinary operation where an incorrect module is selected. Thus, the self-testing arbiter with a high speed and a simple hardware configuration can be realized.

Trustworthy bus arbiter by alternate-data retry

A simple trustworthy bus arbiter by alternate-data retry is proposed. Trustworthiness is considered to be such a property that system responses are always trustworthy whether there exist faults or not in the system. The arbiter has two phase operations to select a parallel decision decentralized arbiter which is used in Futurebus, MultibusII and so on. The presented scheme does not permit that two or more modules are selected as bus masters to cause a fatal system operation. The arbiter presented by alternate-data retry is operated in a specially defined Id code space. Three self complementary-codes named complementary mirrored-code, reversible-ordered-code and continuous two-bit changing code are presented to be applied to the proposed arbiter.<<ETX>>