Yoshiaki Takemura

3-D device modeling for SRAM soft-error immunity and tolerance analysis

Soft-error tolerance of static random-access memory (SRAM) devices has been predicted by using three-dimensional (3-D) and time-dependent device simulation in conjunction with circuit simulation. An inverter model developed for 3-D device simulation is described, along with the analysis of the inverters device response as a function of time. The output thus obtained was applied as an input voltage source in circuit simulation of unit SRAM cell and the stability of this bistable circuit is studied on that basis. The effects on soft-error immunity of changes in alpha-particle injection conditions and in load resistance and capacitance are described. The validity of the presented model is examined through comparison of the bit-error-rate dependence on incident angle of alpha particles to that of measured rates. To simulate the angular dependence, we introduce statistical distribution models for alpha-particle energy, position of incidence on the device surface, and angle of incident. Results of device/circuit simulation carried out with many sets of energy, position, and angle are presented. Reasonable agreement between results of simulation and experimental data without the use of adjustment parameters is demonstrated. A map of soft-error tolerance on the CR plane with critical charge Q/sub c/ as a parameter is presented and its derivation explained. An analytic expression for the tolerance is clarified by proposing an equivalent circuit model for the simulation of alpha-particle injection at the output node in an inverter circuit. Inverter modeling is shown to be essential to obtaining SRAM soft-error tolerance to high degrees of accuracy.

Bipolar-Mode Multibit Soft-Error-Mechanism Analysis of SRAMs by Three-Dimensional Device Simulation

A bipolar-mode multibit soft-error mechanism in static random-access memory (SRAM) devices has been explored by utilizing a 3D device simulation of an inverter constructed with a driver n-MOSFET, a load resistor, and capacitors. Generally, a well tap was not set at every SRAM unit cell so as to increase the packing density. We have introduced a model structure where a p-well for arranging the driver n-MOSFET in a CMOS inverter does not have the well tap in the analyzed cell, and we have studied the inverter action when a drain junction of the n-MOSFET in an OFF-state is hit by an alpha -particle. We found that the p-well is forwardly biased by generated excess carriers. The forward bias at the p-well switches the n-MOSFET from the OFF-to the ON-state, like an on action of an n-p-n transistor, and the output potential of the inverter changes from high to low. This bias change results in a flip on the state of the SRAM unit cell. When a series of n-MOSFETs (or p-MOSFETs) is arranged in the same well and the well tap is not arranged in every unit cell, the switch-on action of the MOSFET is sequentially induced, like a chain reaction. We have developed a multidrain model by adding a p-n junction around the n-MOSFET in the p-well and have successfully demonstrated the chain reaction. In addition, we have demonstrated the soft-error occurrence in an unit cell with the help of circuit simulation. This is the mechanism of multiple soft errors by the bipolar-mode operation. A key factor for evaluating the tolerance of the bipolar-mode soft error is a forwardly biased time at the well (i.e., a well-floating time). The well-floating time (tfloat) is dependent on an initial charge (Qi) in the depletion layer and a resistance (-Rwell) between the well and the tap. The tfloat has been precisely analyzed as functions of Qi and -Rwell, and a critical charge, defined by Qi over which the memory state is flipped, has been clarified for single-and two-bit errors.

Three-Dimensional Capacitance Analysis in an SRAM Cell

l. Introduction As the packing density in ULSIs increases, the interconnect delay becomes a serious problem in achieving high-speed operation. Thus, we need to accurately estimate the interconnect capacitance and design a 3-dimensional (3D) layout to minimize the interconnect capacitance. However, 3D analysis requires long CPU time and large memory area. Therefore, in an effort to reduce the design period of ULSIs, 2D analysis has been performed for the main cross sections of the whole interconnect structure. But this analysis includes effor because it does not take into account the 3D effects [] inherent in a real structure. And this type of analysis cannot be applied for some complex structures. Thus, we analyzed the whole 3D interconnect capacitance in an SRAM cell. Our analysis used Greens function method, which does not require large computational resources. Three-dimensional effects are included in the whole-structure calculation, and all capacitances among conductors can be obtained simultaneously. In this paper, we will report novel 3D effects and examine them in detail.

Calculation of hopping-conduction energy of holes in SiO2 based on molecular orbital theory

Abstract We have developed a new molecular-orbital (MO)-theory-based procedure for calculating activation energies for hole-hopping in dielectrics. The hole-hopping is assumed to consist of two steps. First, the hole hops directly from one trap site to another by electronic excitation without changing atomic structure. Then, the atomic structure gradually relaxes as the hole remains at the newly trapped site. We calculated the excitation energy for hopping to both the nearest-neighbor site and second-nearest-neighbor site in SiO 2 . This calculation covered two types of trap sites: O atom (2p lone-pair MO) and O-vacancy (Si–Si bonding MO). The calculation showed that (1) the energy for O-to-O-vacancy nearest-neighbor site hopping was 1.55 eV, which was 1.29 eV lower than that for O-to-O hopping; and (2) the energies for O-to-O-vacancy and O-to-O second-nearest-neighbor hopping were higher than those for nearest-neighbor hopping. This technique will be a useful tool for understanding atomistic-scale hole conduction in oxides and is applicable to other dielectrics such as nitrides and oxynitrides.

Two-dimensional CVD profile simulator based on ballistic transport and reaction model

We have extended the two-dimensional deposition simulator with a micrometer feature scale based on the ballistic transport and reaction model originally developed by Cale et al. (1993) to include a scheme to inhibit and/or accelerate the deposition reaction stemming from the product gases. We have also improved the algorithm used to calculate a self-consistent gas flux distribution on micro features at each step in the simulation. Application of this deposition simulator to seven CVD systems for ULSI usage showed good agreement between the calculated and experimental feature profiles. The validity of the reactive sticking coefficients role as a general descriptor for step coverage characteristics was thoroughly examined using these simulated results and we concluded that the intrinsic reaction mechanism is more reliable than the sticking coefficient for all CVD characteristics. Molecular orbital calculation was also demonstrated to be extremely helpful in clarifying the intrinsic deposition mechanism.

Improvement of silicon dioxide integrity against hole-related breakdown with the incorporation of foreign atoms: molecular orbital examination

The mechanism for the improvement of gate oxide integrity through the incorporation of nitrogen atoms was examined in terms of molecular orbital theory by considering the chemical bond changes that accompany hole trapping and which cause degradation of the oxide. We found that the robustness against hot-hole injection was significantly improved by the formation of the N/spl equiv/Si/sub 3/ structure in the oxide.