Kenichi Osada

Development of a CAD tool for 3D-FPGAs

This paper presents a newly developed computer-aided design (CAD) tool for 3-dimensional field programmable gate arrays (3D-FPGAs). With this tool, primary inputs/outputs (I/Os) are packed in the configurable logic blocks (CLBs) and placed all over the 3D-FPGA. Moreover, rectangular parallelepiped confinement (RPC) and A-star (A∗) search algorithms are applied to perform 3D routing, which is about 9.0 times faster than the one not introducing the algorithms, without degrading the routing quality.

Performance comparison of 2D and 3D FPGAs using true-3D CAD tool

3-dimensional (3D) integration is imperative for the future of semiconductor devices. The 3D field-programmable gate array (FPGA) is one of the killer applications in this field because large-scale FPGA requires numerous wire segments that conventional 2D integration cannot deal with. We have developed a true-3D computer-aided design (CAD) tool for the 3D FPGA and have quantitatively compared its performance against that of a 2D FPGA. Experimental results indicate that the 3D FPGA is superior to 2D FPGA in terms of both smaller critical path delay and smaller area.