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Dive into the research topics where Yoshihide Sugiura is active.

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Featured researches published by Yoshihide Sugiura.


Microprocessors and Microsystems | 1990

Speed tunable finite state machine compiler: ZEPHCAD

Hitomi Sato; Yoshihide Sugiura; Masahiro Fujita

Abstract The paper describes a personal computer based state machine compiler. This system transforms the finite state machine description, Boolean equations or truth table into net lists of a CMOS gate array or standard cell. A feature of this system is the capability to tune the circuit speed from the user side by selecting the number of logic levels when running the system. Benchmark results are included.


Japanese Journal of Applied Physics | 1980

A 3000-Gate CMOS Masterslice LSI

Mitsumasa Ashida; Ryusuke Hoshikawa; Nobutake Matsumura; Jun-ichi Ishii; Hiroaki Ichikawa; Yoshihide Sugiura; Katsuyuki Inayosh

A new CMOS masterslice LSI has been developed. This LSI adopts silicon gate CMOS of 3.6 µm gate length and double layer metal interconnection process. It can take up to 3000 effective gates without any special cooling requirement. The average propagation delay time is 7 ns/gate and the power dissipation of an LSI is 50 mW at 10 MHz operation. By suitable DA support, it becomes possible to develop LSIs in quick turnaround time avoiding design changes or errors.


Archive | 1990

Learning system in a neuron computer

Hideki Yoshizawa; Hiroki Iciki; Hideki Kato; Kazuo Asakawa; Yoshihide Sugiura; Hiroyuki Tsuzuki; Hideichi Endoh; Takashi Kawasaki; Toshiharu Matsuda; Hiromu Iwamoto; Chikara Tsuchiya; Katsuya Ishikawa


Archive | 1989

Neurocomputer with analog signal bus

Hideki Yoshizawa; Hiroki Iciki; Hideki Kato; Yoshihide Sugiura; Kazuo Asakawa; Hiroyuki Tsuzuki; Hideichi Endo; Takashi Kawasaki; Toshiharu Matsuda; Chikara Tsuchiya; Katsuya Ishikawa; Hiromu Iwamoto


Archive | 1979

Complementary mis-semiconductor integrated circuits

Nobutake Matsumura; Ryusuke Hoshikawa; Yoshihide Sugiura; Hiroaki Ichikawa; Syoji Sato


Archive | 1990

Error absorbing system in a neuron computer

Hideki Yoshizawa; Hiroki Iciki; Hideki Kato; Kazuo Asakawa; Yoshihide Sugiura; Hiroyuki Tsuzuki; Hideichi Endoh; Takashi Kawasaki; Toshiharu Matsuda; Hiromu Iwamoto; Chikara Tsuchiya; Katsuya Ishikawa


Archive | 1980

Semiconductor integrated circuit device including a master slice and method of making the same

Yoshihide Sugiura; Hiroaki Ichikawa; Nobutake Matsumura; Nobuo Sasaki


Archive | 1990

Fehler absorbierendes System in einem neuronalen Rechner Error absorbing system in a neural computer

Hideki Yoshizawa; Hiroki Iciki; Hideki Kato; Kazuo Asakawa; Yoshihide Sugiura; Hiroyuki Tsuzuki; Hideichi Endoh; Takashi Kawasaki; Toshiharu Matsuda; Hiromu Iwamoto; Chikara Tsuchiya; Katsuya Ishikawa


Archive | 1989

Neuronenrechner neurons computer

Hideki Yoshizawa; Hiroki Iciki; Hideki Kato; Yoshihide Sugiura; Kazuo Asakawa; Hiroyuki Tsuzuki; Hideichi Endo; Takashi Kawasaki; Toshiharu Matsuda; Chikara Tsuchiya; Katsuya Ishikawa; Hiromu Iwamoto


Archive | 1989

Neuronarchitektur Neuro Architecture

Hiroyuki Tsuzuki; Hideichi Endo; Takashi Kawasaki; Toshiharu Matsuda; Kazuo Fujitsu Limited Asakawa; Hideki Kato; Hideki Yoshizawa; Hiroki Iciki; Hiromu Iwamoto; Chikara Tsuchiya; Katsuya Fujitsu Limit Ishikawa; Yoshihide Sugiura

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