Yoshihiko Toyoda

Preparation of SiO2 Film by Photo-Induced Chemical Vapor Deposition Using a Deuterium Lamp and Its Annealing Effect

Silicon dioxide thin films have been prepared at low temperatures from SiH4 and O2 by direct photo-induced CVD using a deuterium lamp. The growth rate is 75 A/min at 84°C while no growth occurs below 180°C without deuterium lamp irradiation. UV and VUV light irradiation and an increase of the substrate temperature have effects of increasing the refractive index, and decreasing H incorporation and the amount of the oxide charge. The photo-CVD films deposited above 180°C show refractive indices of 1.45–1.46. Annealing in an O2 environment decreases the infrared absorptions due to Si–H stretching, Si–OH deformation and Si2O3 bondings as well as the oxide charge. The activation energies of the Si–H, the Si–OH deformation, the Si2O3 and the oxide charge obtained from the annealing characteristics are 0.18–0.19, 0.12, 0.19 and 0.12–0.13 eV, respectively. The reduction of Si–OH deformation absorption is considered to be closely related to the reduction of oxide charge.

Highly conductive TiO2 thin films prepared by EB-modification

Abstract Changes in TiO 2 thin films caused by electron-beam (EB) bombardment have been investigated by measuring their structural, electrical and optical properties. The TiO 2 films of 500 nm thickness were deposited on fused silica substrates by the EB-evaporation technique. These as-deposited films are in a highly insulating amorphous state (more than 10 11 Ω m). By using an EB of 10 kV and 30 mA, the as-deposited film is modified to be in a crystalline (anatase) state with a low resistivity of less than 5 × 10 −4 Ω m.

Stacking fault expansion from basal plane dislocations converted into threading edge dislocations in 4H-SiC epilayers under high current stress

We evaluate the stacking faults (SFs) expansion from basal plane dislocations (BPDs) converted into threading edge dislocations (TEDs) under the current stress to the pn devices and analyzed the nucleation site of the SF by combined polishing, chemical etching in molten KOH, photoluminescence imaging, Focus ion beam, transmission electron microscopy, and Time-of-Flight secondary ion mass spectrometer techniques. It was found that the formation of SFs occurs upon the current stress levels of 400 A/cm2 where the diode area is not including BPDs in the drift layer after the high current stress, and the high current stress increases the SFs expansion density. It was also found the dependence of the junction temperature. The estimated activation energy for the expansion of SFs is Ea = 0.46 eV. The SF extends from the conversion point of the BPD into the TED within buffer layer. Even though BPDs converted into TEDs within the high doped buffer layer, SFs expand under high current stress.

Driving Force of Stacking Fault Expansion in 4H-SiC PN Diode by In Situ Electroluminescence Imaging

We evaluate the velocity of stacking faults (SFs) expansion under various current and temperature levels on the pn diodes by electroluminescence (EL) observation in situ. The driving force of the SFs expansion is analyzed on the basis of the experimental results. The velocity of the SFs expansion increases in proportional to the current density at the every junction temperature levels. The activation energy for the velocity of the SFs expansion is estimated.

Electromigration resistance of TiWN/Cu/TiWN interconnections

Abstract The present paper describes the activation energy for electromigration damage (EMD) of the Cu multilayer interconnection. The Cu multilayer (TiWN/Cu/TiWN) interconnections (width ∼ 0.7 μm) were fabricated by the Ar-sputtering method. The electromigration (EM) resistance measurements were carried out on a wafer level. The AlCu multilayer (TiN/AlCu/TiN/Ti) interconnections were also prepared by the conventional process, and EM resistance was evaluated by the same method. A current density applied to the interconnection was in the range of 16 to 24 MA/cm 2 . After the EM test, voids were formed in the Cu layer of the TiWN/Cu/TiWN multilayer, and the Cu hillocks were formed at the anode side. The activation energies for electromigration damage (EMD) of the Cu and AlCu interconnections were 0.97 and 0.62 eV, respectively. The activation energies and medium time to failures (MTF) of Cu and AlCu showed that the lifetime of the Cu interconnections at 110°C was about three orders of magnitude longer than that of AlCu.

Ferroelectric liquid crystal cell having gray scale for high-speed spatial light modulator

Gray scale was obtained with a ferroelectric liquid crystal (FLC) cell in which the twisted state of FLC molecules is gradually unwound by an applied voltage. The cell has an extinction ratio of 60 at 632. 8 nm and a response time of 300 jtsec. A spatial light modulator (SLM) with 256 x 256 pixels was fabricated by incorporating the FLC cell with an amorphous silicon thin film transistor array. This offers us a promising technology to realize a FLC-SLM with gray scale a fast frame time of 300 psec and a pixel number as large as 1000 x 1000.

Demonstration of High Quality 4H-SiC Epitaxial Growth with Extremely Low Basal Plane Dislocation Density

SiC epitaxial layer with low basal plane dislocation (BPD) density of 0.2/cm2 was successfully grown under higher C/Si ratio, which is found on the investigation about growth conditions. In order to study conversion mechanism of BPDs to threading edge dislocations (TEDs), angles between directions of BPD lines on a substrate and that of moving edges of steps ([11-2) during growth were examined. Consequently, it was revealed that almost 98% of BPDs are converted to TEDs for the case of the absolute angles above 45°. This high conversion ratio is considered to be induced by enhanced lateral growth under the higher C/Si ratio condition.

Designing and Fabrication of the VLD Edge Termination for 3.3 kV SiC SBD

Edge termination guaranteeing high breakdown voltage and robustness in its fabrication are required in SiC power devices. We newly employed the VLD edge termination for 3.3 kV-rated SiC SBDs, which was formed by Al ion implantation using a resist mask having a varying thickness. The breakdown voltage is recorded to be over 96% of the parallel-plane breakdown voltage, and the reverse bias characteristics are well accorded with the result of TCAD simulation.

Influence of Growth Pressure and Addition of HCl Gas on Growth Rate of 4H-SiC Epitaxy

The reduction of the growth pressure was demonstrated to have the same effect as the addition of chloride-containing gas on preventing the Si nucleation and the epitaxy with high growth rate (>50 μm/h) was achieved by using the decreasing pressure condition in a horizontal CVD reactor without chloride-containing gas. The quality of a 30-μm-thick epilayer grown with 40 μm/h was also investigated. Downfall and triangle defect density in the layer was as low as 0.16 /cm2, indicating that a high quality epitaxial wafer can be easily obtained under the condition with high throughput in the sinple CVD system.

Properties of a SiC Schottky Barrier Diode Fabricated with a Thin Substrate

One of the attractive methods to reduce the differential resistance of SiC devices is to make the thickness of a SiC substrate thinner [1]. Therefore, we fabricated SiC Schottky barrier diode (SBD) chips with a thickness below 150 μm and the properties of the SiC-SBD chips were measured. It was confirmed that the junction temperature of the thin SiC-SBD chips was decreased by the combination of the reduction in a thickness of the chip and the back side bonding of the chip using a material with high thermal conductivity. Moreover, it was confirmed that the potential of the thin SiC-SBD chip for the surge current capacity could be enhanced to combine the thin SiC-SBD chip with the back side bonding which has high thermal conductivity.