Hiroaki Sumitani

High aspect pattern fabrication by nano imprint lithography using fine diamond mold

Nano imprint lithography is an attractive fine lithographic method to obtain nano patterns by using low cost process and materials., Various applications have been demonstrated to utilize this fine method. One of the advantages of nano imprint lithography is that a wet development process is not required, which sometimes causes sticking errors by surface tension during wet development process. On the other hand, there is no fear of such defects by imprint lithography because a resist is mechanically deformed and released. We have demonstrated high aspect ratio pattern fabrication as high as 6.0 with 200nm in line width. But the mold is fabricated using thin Si substrate and anisotropic wet chemical etching, which cannot fabricate voluntary patterns by crystalline axis dependence.

Sub-hundred nanometre pitch measurements using an AFM with differential laser interferometers for designing usable lateral scales

We have developed a new atomic force microscope with differential laser interferometers (DLI-AFM), carried out test measurements of the prototype 1D-grating standards with pitches of 100, 80, 60 and 50 nm using the DLI-AFM and evaluated the uncertainty in the pitch measurements. In the procedures of the pitch calculation, two types of definitions of the peak positions, the centre of gravity method, and the zero-crossing method, were compared. The zero-crossing method was adopted in this study since the standard deviation of pitches by the zero-crossing method was smaller than that by the centre of gravity method. The expanded uncertainty (k = 2) was approximately 0.20 nm and was only 0.4% for the nominal pitch of 50 nm. We propose a design of usable 1D-grating standards as certified reference materials.

Alignment mark optimization to reduce tool and wafer induced shift for XRA-1000

Summary form only given. As the most critical semiconductor device geometry shrinks down to 100 nm order, requirements for overlay accuracy also become increasingly critical in the actual semiconductor manufacturing process. Factors in overlay error (especially, alignment error) originate in the interaction of processes and tools. It is therefore necessary to improve alignment accuracy from both the process and the tool sides. The alignment errors can be separated into Tool Induced Shift (TIS), Wafer Induced Shift (WIS), and TIS-WIS interaction. The authors consider the optimization of the alignment mark in order to reduce not only TIS, but also WIS for the XRA-1000, which is the volume production stepper of proximity X-ray lithography.

Low on-resistance 1.2 kV 4H-SiC MOSFETs integrated with current sensor

4H-SiC MOSFETs integrated with a current sensor have been fabricated for the first time. The MOSFET shows superior characteristics with a specific on-resistance of 3.7 mΩcm2 and a blocking voltage of 1.4 kV. The deviation of the current ratio (Imain/Isense) stays within 10% in the temperature range between 25°C and 175°C, which is desirable for the current sensor of high power devices. Furthermore, the main current shut-off operation at an over-current detected using the current sensor has been demonstrated successfully.

Replicating characteristics by SR lithography

Process optimization and pattern replication on various substrates by synchrotron radiation lithography was carried out to evaluate the problems for 0.15 micrometers level resists patters for 1-Gbit dynamic random access memory. It was found that the exposure latitude was rather restricted by the resist residue remaining between lines (scum) and the pattern collapse than the normally used +/- 10-percent critical dimensions. A simple Fresnel diffraction calculation including the phase-shifting effect and mask contrast showed that the occurrence of the scum was mainly determined by the optical images of x-rays, and could not be significantly improved by the resist process condition. We used the mask/wafer proximity gap of 20 micrometers to get a good optical image and 5000-angstrom resist thickness to suppress the pattern collapse. On the other hand, the replicating characteristics on the light element substrates were similar to that on the Si substrate, especially good on the SiN substrate, but the residues caused by secondary electrons ont he metal substrates and the catalytic reaction on the Pt substrate were observed. It was shown that protection layers could suppress those residues and serve a good pattern profile.

Fabrication and Performance of 1.2 kV, 12.9 mΩcm2 4H-SiC Epilayer Channel MOSFET

4H-SiC epilayer channel MOSFETs are fabricated. The MOSFETs have an n- epilayer channel which improves the surface where the MOS channel is formed. By the optimization of the epilayer channel and the MOSFET cell structure, an ON-resistance of 12.9 mcm2 is obtained at VG = 12 V (Eox = 2.9 MV/cm). A normally-OFF operation and stable avalanche breakdown is obtained at the drain voltage larger than 1.2 kV. Both the ON-resistance and the breakdown voltage increase slightly with an increase in temperature. This behavior is favorable for high power operation. By the evaluation of the control MOSFETs with n+ implanted channel, the resistivity of the MOS channel is estimated. The MOS channel resistivity is proportional to the channel length and it corresponds to an effective channel mobility of about 20 cm2/Vs.

Investigation of Cell Structure and Doping for Low-On-Resistance SiC Metal–Oxide–Semiconductor Field-Effect Transistors with Blocking Voltage of 3300 V

We have investigated the effect of n-type doping into the junction field-effect transistor region (JFET doping) on the static characteristics of 3300-V-class 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs). The JFET doping technique is significantly effective in reducing the on-resistance of SiC MOSFETs without degradation of the blocking characteristics when the MOS cells are properly designed. The JFET doping reduces the temperature coefficient of the resistance in the JFET region, leading to lower on-resistance of the SiC MOSFETs at high temperatures.

Demonstration of High Quality 4H-SiC Epitaxial Growth with Extremely Low Basal Plane Dislocation Density

SiC epitaxial layer with low basal plane dislocation (BPD) density of 0.2/cm2 was successfully grown under higher C/Si ratio, which is found on the investigation about growth conditions. In order to study conversion mechanism of BPDs to threading edge dislocations (TEDs), angles between directions of BPD lines on a substrate and that of moving edges of steps ([11-2) during growth were examined. Consequently, it was revealed that almost 98% of BPDs are converted to TEDs for the case of the absolute angles above 45°. This high conversion ratio is considered to be induced by enhanced lateral growth under the higher C/Si ratio condition.

Influence of Growth Pressure and Addition of HCl Gas on Growth Rate of 4H-SiC Epitaxy

The reduction of the growth pressure was demonstrated to have the same effect as the addition of chloride-containing gas on preventing the Si nucleation and the epitaxy with high growth rate (>50 μm/h) was achieved by using the decreasing pressure condition in a horizontal CVD reactor without chloride-containing gas. The quality of a 30-μm-thick epilayer grown with 40 μm/h was also investigated. Downfall and triangle defect density in the layer was as low as 0.16 /cm2, indicating that a high quality epitaxial wafer can be easily obtained under the condition with high throughput in the sinple CVD system.

Properties of a SiC Schottky Barrier Diode Fabricated with a Thin Substrate

One of the attractive methods to reduce the differential resistance of SiC devices is to make the thickness of a SiC substrate thinner [1]. Therefore, we fabricated SiC Schottky barrier diode (SBD) chips with a thickness below 150 μm and the properties of the SiC-SBD chips were measured. It was confirmed that the junction temperature of the thin SiC-SBD chips was decreased by the combination of the reduction in a thickness of the chip and the back side bonding of the chip using a material with high thermal conductivity. Moreover, it was confirmed that the potential of the thin SiC-SBD chip for the surge current capacity could be enhanced to combine the thin SiC-SBD chip with the back side bonding which has high thermal conductivity.