Yoshihiko Yasu

An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler

Power efficient SoC design for embedded applications requires several independent power-domains where the power of unused blocks can be turned off. An SoC for mobile phones defines 23 hierarchical power domains but most of the power domains are assigned for peripheral IPs that mainly use low-leakage high-Vt transistors. Since high-performance multiprocessor SoCs use leaky low-Vt transistors for CPU sections, leakage power savings of these CPU sections is a primary objective. We develop an SoC with 8 processor cores and 8 user RAMs (1 per core) targeted for power-efficient high-performance embedded applications. We assign these 16 blocks to separate power domains so that they can be independently be powered off. A resume mode is also introduced where the power of the CPU is off and the user RAM is on for fast resume operation. An automatic parallelizing compiler schedules tasks for each CPU core and also performs power management for each CPU core. With the help of this compiler, each processor core can operate at a different frequency or even dynamically stop the clock to maintain processing performance while reducing average operating power consumption. The compiler also executes power-off control of unnecessary CPU cores.

Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs

Hierarchical power distribution with a power tree has been developed. The key features are a power-tree structure with three power-tree management rules and a distributed common power domain implementation. The hierarchical power distribution supports a fine-grained power gating with dozens of power domains, which is analogous to a fine-grained clock gating. Leakage currents of a 1 000 000-gate power domain were effectively reduced to 1/4000 in multi-CPU SoCs with minimal area overhead

In-Situ Measurement of Supply-Noise Maps with Millivolt Accuracy and Nanosecond-Order Time Resolution

An in-situ measurement scheme for supply-noise maps under running applications in product-level LSIs was developed. This scheme was used to successfully measure 69-mV local supply noise with 5-ns time resolution in a 3G cellular phone processor. It will thus help in designing power-supply networks and visibly verifying the quality of a power supply

A 4-Mb pseudo SRAM operating at 2.6+or-1 V with 3- mu A data retention current

A 4-Mb pseudo static RAM (PSRAM) suitable for universal battery usage is described. The wide voltage range, 2.6+or-1 V, is set to target the power supply voltage of the PSRAM considering various voltage levels and charging-discharging characteristics of batteries. A double-to-single automatically switchable booster is developed to provide the wide voltage range operation. To reduce the power dissipation of data retention for battery usage a low-power back-bias generator with a new substrate-level sensor and a temperature-dependent self-refresh timer with a unique internal refresh control scheme are demonstrated. A PSRAM operation ranging from 1 V to more than 5 V was obtained and a 3- mu A data retention current was realized at room temperature in contrast with 7 mu A at 70 degrees C and V/sub cc/ of 2.6 V. This PSRAM allows a 20-Mbyte RAM disk to retain data for two months with a single lithium battery. >

In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution

An in situ measurement scheme for generating supply-noise maps, which can be conducted while running applications in product-level LSIs, was developed. The design of the on-chip voltage sampling probe is based on a simple ring oscillator, which converts local supply difference between VDD and VSS to oscillation-frequency deviation. High measurement accuracy is achieved by off-chip digital signal processing and calibration. This scheme was used to successfully measure 69-mV local supply noise with 5-ns time resolution in a 3G-cellular-phone processor. It will thus help in designing power-supply networks and in visually verifying the quality of a power supply

/spl mu/I/O architecture for 0.13-/spl mu/m wide-voltage-range system-on-a-package (SoP) designs

To provide low-cost system solutions together with a 0.13-/spl mu/m dual-t/sub ox/ CMOS and multi-chip package (MCP) technologies, a new, so-called /spl mu/I/O architecture was developed. The /spl mu/I/O provides a common interface throughout the module and, thus, enables high design reusability and hierarchical I/O design for MCPs. The /spl mu/I/O includes a signal-level converter for integrating wide-voltage-range (0.75-1.3 or 1.5-3.6 V) circuit blocks, and a signal wall function for turning off each block independently - without invalid signal transmission - by using an internal power switch.

A low-power wide-range clock synchronizer with predictive-delay-adjustment scheme for continuous voltage scaling in DVFS control

A “wide-range voltage-and-frequency clock synchronizer” (WRCS) for maintaining synchronization during voltage-scaling transition during dynamic voltage-and-frequency scaling (DVFS) was developed. The key feature of the WRCS is so-called predictive-delay-adjustment (PDA) scheme based on a relative skew measure. The PDA scheme reduces the area of the WRCS by 77%. The area of the fabricated WRCS in a 40-nm CMOS is only 5.65×10−3 mm2. It was demonstrated for the first time that measured jitter is suppressed to less than 6.8% of clock period in the case of wide-range voltage variation (0.8–1.55 V) and wide frequency range (100 MHz–1 GHz). Moreover, current dissipation of the WRCS is only 0.48 mA at 1.1-V 100-MHz operation.

Dynamic voltage boost (DVB) method for improving power integrity of low-power multi-processor SoCs

We propose a dynamic voltage boosting (DVB) method for improving performance by slightly boosting voltage within a withstand voltage. We measured an improvement of 44%voltage drop with about 10 % area overhead in a 65 nm CMOS. This DVB method combined with a series power gating can be used to achieve high performance for low-cost low-power SoCs in advanced process technology.

Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor

Hierarchical power distribution using a power tree is developed. It supports fine-grained power gating with dozens of power domains like fine-grained clock gating and effectively reduces leakage currents for 1-million-gate power domains to 1/4000 in multi-CPU processors with minimal area overhead. This paper demonstrates the integration of 20 power domains in a 90nm single-chip 3G cellular phone processor