Koichiro Ishibashi

A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias

Substrate bias is continuously controlled from -1.5 V (backward bias) to 0.5 V (forward bias) to compensate for fabrication fluctuation, supply voltage variation, and operating temperature variation. A speed-adaptive threshold-voltage (SA-Vt) CMOS with forward bias is used in a 4.3M transistor microprocessor. The SA-Vt CMOS with forward bias occupies 320/spl times/400 /spl mu/m/sup 2/ and consumes 4 mA. The processor provides 400 VAX MIPS at 1.5 to 1.8 V with 320 to 380mW dissipation. It achieves >1000-MIPS/W performance.

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-mum2 SRAM cell with a beta ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology

16.7 fA/cell tunnel-leakage-suppressed 16 Mb SRAM for handling cosmic-ray-induced multi-errors

A 16 Mb SRAM based on an electric-field-relaxed scheme and an alternate error checking and correction architecture for handling cosmic-ray-induced multi-errors is realized in 0.13 /spl mu/m CMOS technology. The IC has a 16.7 fA/cell standby current, a cell size of 2.06 /spl mu/m/sup 2/ and a 99.5% smaller SER.

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2%.

Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability

6T-SRAM cells in the sub-100 nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (/spl sigma//sub v/spl I.bar/Local/). To achieve high-yield SRAM arrays in presence of random /spl sigma//sub v/spl I.bar/Local/ component, we propose worst-case analysis that determines the boundary of the stable Vth region for the SRAM read/write DC margin (Vth curve). Applying this to our original 65 nm SPICE model, we demonstrate typical behavior of the Vth curve and show new criteria for discussing SRAM array stability with Vth variability.

A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits

We propose a new design scheme to improve the SRAM read and write operation margins in the presence of a large Vth variability. By applying this scheme to a 0.494 mum2 SRAM cell with a beta ratio of 1, which is an aggressively small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth value using a 65 nm LSTP CMOS technology

A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond

In this paper, we proposed a soft-error hardened latch (SEH-latch) scheme that has an error correction function in the fine process. To achieve this, we designed two types of SEH-latch circuits and a standard latch circuit using 130 nm 2-well, and also 90 nm 2-well CMOS processes. The proposed circuit demonstrated 2-order higher immunity through a radiation test using /spl alpha/-particles, and 1-order higher immunity through neutron irradiation.

Cosmic-ray immune latch circuit for 90nm technology and beyond

A cosmic-ray immune latch circuit is presented. The storage node is separated into three electrodes, and the soft error on one node can be corrected by the other two, even if there is a large and long-lasting influx of radiation-induced charges. The circuit is proved to have significant tolerance by utilizing a test chip.

A 9/spl mu/W 50MHz 32b adder using a self-adjusted forward body bias in SoCs

This 32b adder in a 0.13/spl mu/m CMOS process consumes 9/spl mu/W at 50MHz and 0.3V and operates at 500MHz at 0.6V. Forward body biases are self-adjusted to minimize the threshold voltage and reduce PVT dependence. The power of the SoC can be reduced to 1/4 that of standard CMOS by gating the forward body bias in the IP blocks.

A 1.92 μs-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors

A technique for controlling rush current and wake-up time of thick-gate-oxide power switches is described. Suppressing the variation of rush current on PVT allows shorter wake-up times, which can reduce leakage currents in a mobile processor. Wake-up takes 1.92 μs and leakage current is reduced by 96.9% in an application CPU domain. Probing the rush current indicated accurate control by the technique.