Yoshihiro Fujita

A 3.84 GIPS integrated memory array processor LSI with 64 processing elements and 2 Mb SRAM

An integrated memory array processor (IMAP) LSI has peak performance of 3.84 GIPS and is suitable for high-speed, low-level image processing (LIP). Keys to performance are: integration of 64 simple processing elements (PEs) and 2 Mb SRAM with 128 b I/O, and single-instruction stream multiple-data stream (SIMD) parallel processing by use of 1.28 GB/s on-chip processor-memory bandwidth. A large number of active sense amplifiers ordinarily used in a wide memory bandwidth creates the problem of large power consumption. The number of active sense amplifiers here is reduced by a factor of 4 by accessing half of each word at a time, but accessing it at twice the speed of the PE clock. This keeps power consumption low. Each memory block can perform indexed addressing within its pages. This capability contributes to IMAP flexibility and efficiency in LIP. To raise yield, the architecture employs 4-way block replacement redundancy. IMAP is fabricated in 0.55 /spl mu/m BiCMOS 2-layer metal process technology. >

A 250000-pixel image sensor with FET amplification at each pixel for high-speed television cameras

An amplified MOS imager (AMI) for use in each pixel in a high-speed TV camera is discussed. The AMI performs such functions as amplification, readout, and resetting independently and completely. Thus the AMI is easier to operate and completely free from image lag, and has relatively little smear (2*10/sup -5/) compared with other devices. The AMI can also handle both hole and electron signals when a photoconductive layer is laminated on its surface. The image area dimensions are 8.8 mm (H)*6.6 mm (V) with 510 (H)*490 (V) pixels. Each pixel has an FET amplifier that enhances signal current 100*immediately after receiving the incident light. A source-follower is used for output signal linearity. The AMI is equipped with three horizontally aligned output lines, each operated at a horizontal clock rate of 30 MHz. The total sampling frequency can be 90 MHz, but the device in this television camera application operates at a sampling frequency of 57 MHz.<<ETX>>

A 10 GIPS SIMD processor for PC-based real time vision applications -architecture, algorithm implementation and language support

This paper describes hardware implementation and software environment of a one-dimensional SIMD processor, IMAP-VISION. IMAP-VISION board is a single-slot PCI-bus board designed for PC-based real-time vision applications. The SIMD processor consists of 256 8-bit linear processor array and has 10.24 GIPS peak performance. In this paper, some detailed algorithm implementations, those which make use of IMAP-VISION special functions; are described, as well as IMAP-VISION architecture, hardware implementation, performance figures and software environment including high-level language 1DC and graphical user interface.

A compact real-time vision system using integrated memory array processor architecture

This paper describes the real-time vision system (RVS-2) which shows quite high performance for low-level image processing while it is implemented in a one-board type compact size format with small power consumption. The RVS-2 consists of an IMAP board, a video board and a host workstation. The IMAP board consists of eight highly-integrated IMAP LSIs and a dedicated control LSI (RVSC). The IMAP chip integrates 2 Mb image memory and 64 processing elements that operate in the SIMD mode. The RVSC chip performs global data operations efficiently without interactions with the host workstation, as well providing an instruction stream to the IMAP chips. The peak performance of the RVS-2 is 30 GIPS and most of the basic image processing tasks are carried out within about 0.1-0.7 ms, which is about 50-300 times faster than the video frame rate. >

A 7.68 GIPS 3.84 GB/s 1W parallel image processing RAM integrating a 16 Mb DRAM and 128 processors

A parallel image processing RAM (PIP-RAM) integrates a 16 Mb DRAM and 128 processor elements (PEs) on a single chip in 64 Mb DRAM process technology. There are three general design requirements when integrating DRAMs and processors onto a single chip: high-data-rate random access, low-power dissipation, and efficiently synchronized DRAM and processor. The PIP-RAM employs three circuit techniques in response to these requirements: (1) a paged-segmentation accessing (PSA), (2) a clocked low-voltage-swing differential-charge-transfer (CLD), and (3) a multiphase synchronization DRAM control (MSD) that uses a multiple-stage PLL. Large memory capacity and high-data-rate random access achieved by these techniques make the PIP-RAM suitable for image processing of large-scale, full-color pictures.

A 64 parallel integrated memory array processor and a 30 GIPS real-time vision system

Describes a parallel-processor LSI chip (the Integrated Memory Array Processor, IMAP) and a compact real-time vision system (RVS-2). The IMAP integrates 64 8-bit processors, which operate in a SIMD manner, and 2-Mbit image memory on a single chip, and has peak performance of 3.84 GIPS. The RVS-2 consists of 8 IMAPs, a video interface, a control LSI chip (the Real-time Vision System Controller, RVSC) and a host workstation. RVSC is a 16-bit processor which carries out global data operations as well as providing an instruction stream to IMAP processors. In the RVS-2 system, the IMAP processors accomplish data-parallel operations, the RVSC applies global data operations to the results, and the host workstation carries out higher-level recognition tasks using the results obtained by the IMAPs and the RVSC. The peak performance of the RVS-2 is 30 GIPS and most of the basic image processing is carried out in 0.1 to 0.7 ms, which is 50 to 300 times faster the video rate.

IMAP: INTEGRATED MEMORY ARRAY PROCESSOR

This paper presents architectural features and performances for an Integrated Memory Array Processor (IMAP) LSI, which integrates a large capacity memory and a one-dimensional SIMD processor array on a single chip. The IMAP has a conventional memory interface, almost the same as a dual port video RAM with operational input extension. SIMD processing is carried out on the IMAP chip, using an internal processor array, while other higher level processing is concurrently accomplished with external processors through the random access memory port. In addition to the basic IMAP architecture, this paper describes orthogonal IMAP, which has an extended IMAP architecture. The basic IMAP uses a conventional memory cell, while the orthogonal IMAP uses an orthogonal memory for holding images.

An amplified MOS imager suited for image processing

Recent progress in solid-state imaging sensor technology has increased the number of pixels. The increased sensor array size inevitably raises the data rate and leads to difficulties in image processing. Most of these difficulties come from the scanning operation in which spatially adjacent vertical pixels are arranged separately in a time axis. To solve the problem, this amplified MOS imager (AMI) outputs three neighboring lines simultaneously. This permits signals from spatially-adjacent vertical pixels to be handled at the same time. Two advantages made it possible to realize this sensor. One is signal charge amplification to prevent SNR degradation, the other is a non-destructive read-out function. The sensor is fabricated with 0.8 /spl mu/m, double-polysilicon double-aluminum CMOS process technology.<<ETX>>

Advanced Conditional Access System for Digital Broadcasting Receivers Using Metadata

This paper presents an advanced conditional access system (CAS) for digital broadcasting receivers using program-related information called metadata. Digital broadcasting receivers using metadata (DBRM) provide services enhanced by using metadata and content stored in receivers, but it is so easy to edit stored content by using metadata that broadcasters require a content usage control mechanism for DBRM. The advanced CAS provides a secure environment for content and metadata in digital broadcasting receivers by preventing tampering and ensuring that only metadata certified by the broadcaster can be used. To evaluate the advanced CAS, we also developed a smart card and a prototype receiver on a PC. We have demonstrated in an implementation experiment that the advanced CAS can be implemented securely and utilized in broadcasting services using DBRM.

Near-Field Sound-Source Localization Based on a Signed Binary Code

This paper proposes near-field sound-source localization based on crosscorrelation of a signed binary code. The signed binary code eliminates multibit signal processing for simpler implementation. Explicit formulae with near-field assumption are derived for a two microphone scenario and extended to a three microphone case with front-rear discrimination. Adaptive threshold for enabling and disabling source localization is developed for robustness in noisy environment. The proposed sound-source localization algorithm is implemented on a fixed-point DSP. Evaluation results in a robot scenario demonstrate that near-field assumption and front-rear discrimination provides almost 40% improvement in DOA estimation. A correct detection rate of 85% is obtained by a robot in a home environment.