Shin'ichiro Okazaki

A 3.84 GIPS integrated memory array processor LSI with 64 processing elements and 2 Mb SRAM

An integrated memory array processor (IMAP) LSI has peak performance of 3.84 GIPS and is suitable for high-speed, low-level image processing (LIP). Keys to performance are: integration of 64 simple processing elements (PEs) and 2 Mb SRAM with 128 b I/O, and single-instruction stream multiple-data stream (SIMD) parallel processing by use of 1.28 GB/s on-chip processor-memory bandwidth. A large number of active sense amplifiers ordinarily used in a wide memory bandwidth creates the problem of large power consumption. The number of active sense amplifiers here is reduced by a factor of 4 by accessing half of each word at a time, but accessing it at twice the speed of the PE clock. This keeps power consumption low. Each memory block can perform indexed addressing within its pages. This capability contributes to IMAP flexibility and efficiency in LIP. To raise yield, the architecture employs 4-way block replacement redundancy. IMAP is fabricated in 0.55 /spl mu/m BiCMOS 2-layer metal process technology. >

A robust vehicle detecting and tracking system for wet weather conditions using the IMAP-VISION image processing board

We present a robust vehicle detecting and tracking system for highway scenes of both dry and wet weather conditions taken from a forward-looking vehicle mounted camera. The system comprises the potential vehicle search, vehicle validation, and vehicle tracking processes. In order to overcome reduced visibility conditions, image normalization is performed automatically according to input image contrast and a weak edge grouping technique is used for preventing mass detections during the potential vehicle search process. The system runs at a rate of 15 frames/sec using a PC with the IMAP-VISION realtime image processing board. Results of experiments on image sequences of various highway scenes are presented.

A 10 GIPS SIMD processor for PC-based real time vision applications -architecture, algorithm implementation and language support

This paper describes hardware implementation and software environment of a one-dimensional SIMD processor, IMAP-VISION. IMAP-VISION board is a single-slot PCI-bus board designed for PC-based real-time vision applications. The SIMD processor consists of 256 8-bit linear processor array and has 10.24 GIPS peak performance. In this paper, some detailed algorithm implementations, those which make use of IMAP-VISION special functions; are described, as well as IMAP-VISION architecture, hardware implementation, performance figures and software environment including high-level language 1DC and graphical user interface.

A compact real-time vision system using integrated memory array processor architecture

This paper describes the real-time vision system (RVS-2) which shows quite high performance for low-level image processing while it is implemented in a one-board type compact size format with small power consumption. The RVS-2 consists of an IMAP board, a video board and a host workstation. The IMAP board consists of eight highly-integrated IMAP LSIs and a dedicated control LSI (RVSC). The IMAP chip integrates 2 Mb image memory and 64 processing elements that operate in the SIMD mode. The RVSC chip performs global data operations efficiently without interactions with the host workstation, as well providing an instruction stream to the IMAP chips. The peak performance of the RVS-2 is 30 GIPS and most of the basic image processing tasks are carried out within about 0.1-0.7 ms, which is about 50-300 times faster than the video frame rate. >

An Integrated Memory Array Processor for Embedded Image Recognition Systems

Embedded processors for video image recognition in most cases not only need to address the conventional cost (die size and power) versus real-time performance issue, but must also maintain high flexibility due to the immense diversity of recognition targets, situations, and applications. This paper describes IMAP, a highly parallel SIMD linear processor and memory array architecture that addresses these trade-off requirements. By using parallel and systolic algorithmic techniques, but based on a simple linear array architecture, IMAP successfully exploits not only the straightforward per-image row data level parallelism (DLP), but also the inherent DLP of other memory access patterns frequently found in various image recognition tasks, while allowing programming to be done using an explicit parallel C language (1DC). We describe and evaluate IMAP-CE, one of the latest IMAP processors, integrating 128 100 MHz 8 bit 4-way VLIW PEs, 128 2 KByte RAMs, and one 16 bit RISC control processor onto a single chip. The PE instruction set is enhanced to support 1DC code. The die size of IMAP-CE is 11 times11 mm2 integrating 32.7 M transistors, while the power consumption is, on average, approximately 2 watts. IMAP-CE is evaluated mainly by comparing its performance while running 1DC code with that of a 2.4 GHz Intel P4 running optimized C code. Based on the use of parallelizing techniques, benchmark results show a speed increase of up to 20 times for image filter kernels and of 4 times for a full image recognition application

A 64 parallel integrated memory array processor and a 30 GIPS real-time vision system

Describes a parallel-processor LSI chip (the Integrated Memory Array Processor, IMAP) and a compact real-time vision system (RVS-2). The IMAP integrates 64 8-bit processors, which operate in a SIMD manner, and 2-Mbit image memory on a single chip, and has peak performance of 3.84 GIPS. The RVS-2 consists of 8 IMAPs, a video interface, a control LSI chip (the Real-time Vision System Controller, RVSC) and a host workstation. RVSC is a 16-bit processor which carries out global data operations as well as providing an instruction stream to IMAP processors. In the RVS-2 system, the IMAP processors accomplish data-parallel operations, the RVSC applies global data operations to the results, and the host workstation carries out higher-level recognition tasks using the results obtained by the IMAPs and the RVSC. The peak performance of the RVS-2 is 30 GIPS and most of the basic image processing is carried out in 0.1 to 0.7 ms, which is 50 to 300 times faster the video rate.

IMAP: INTEGRATED MEMORY ARRAY PROCESSOR

This paper presents architectural features and performances for an Integrated Memory Array Processor (IMAP) LSI, which integrates a large capacity memory and a one-dimensional SIMD processor array on a single chip. The IMAP has a conventional memory interface, almost the same as a dual port video RAM with operational input extension. SIMD processing is carried out on the IMAP chip, using an internal processor array, while other higher level processing is concurrently accomplished with external processors through the random access memory port. In addition to the basic IMAP architecture, this paper describes orthogonal IMAP, which has an extended IMAP architecture. The basic IMAP uses a conventional memory cell, while the orthogonal IMAP uses an orthogonal memory for holding images.

A low-cost mixed-mode parallel processor architecture for embedded systems

A scalable SIMD/MIMD mixed-mode parallel processor architecture called XC core is proposed to meet the high and diverse performance requirements of embedded multimedia applications. XC core supports both the SIMD and MIMD computing models at low hardware cost by dynamically reconfiguring itself into datapath circuits or control circuits, i.e., trading off between performance and flexibility. A control processor is used to broadcast instructions to a whole SIMD PE (Processing Element) array or to a part of it while assigning a separate program to each PU (Processing Unit), that is mainly composed of the hardware resources of several PEs. RTL synthesis results show that area overhead for reconfiguration is merely 10% of the total area. Benchmark results show that the SIMD mode is effectively achieving high performance towards the regular and massive data parallelism portions of applications, while the MIMD mode enables acceleration of the remaining part of applications whose implementation using a pure highly parallel SIMD architecture would otherwise be impossible. The results show that the XC core design is competitive against more complex processors, with respect to both its cost efficiency as a highly parallel SIMD processor and its flexibility as a multicore MIMD processor, against a wide range of applications.

IMAP-CE: a 51.2 GOPS video rate image processor with 128 VLIW processing elements

IMAP-CE is the fourth generation of a series of SIMD linear processor arrays based on the IMAP (integrated memory array processor) architecture. The aim of IMAP-CE is to provide a compact, cost effective and yet high performance solution for various embedded real-time vision applications, especially for vision based driving assistance applications in the ITS (intelligent transportation system) fields. IMAP-CE integrates 128 VLIW processing elements, and a RISC control processor which provides the single instruction stream for the processor array. The peak performance of IMAP-CE is up to 51.2 GOPS operating under 100 MHz. This paper describes the design features of IMAP-CE, its enhanced instruction set for image processing, and the estimated performance.

A real-time vision system using an integrated memory array processor prototype

This paper describes a real-time vision system (RVS) architecture and performance and its use of an integrated memory array processor (IMAP) prototype. This prototype integrates eight 8-bit processors and a 144-kbit SRAM on a single chip. The RVS was developed with 64 IMAP prototypes connected in series in a 512 processor-system configuration. A host workstation can access the memory on the IMAP prototypes directly through a random access port. Images are inputted and outputted at high speed through serial access ports. The RVS performance is shown in real-time road-image processing and in a neural network simulation, as well as in low-level image processing algorithms, such as filtering, histograms, discrete cosine transform (DCT), and rotation. The RVS image processing is shown to be much faster than the video rate.