Yoshihiro Sato

GaN Power Transistors on Si Substrates for Switching Applications

In this paper, GaN power transistors on Si substrates for power switching application are reported. GaN heterojunction field-effect transistor (HFET) structure on Si is an important configuration in order to realize a low loss and high power devices as well as one of the cost-effective solutions. Current collapse phenomena are discussed for GaN-HFETs on Si substrate, resulting in suppression of the current collapse due to using the conducting Si substrate. Furthermore, attempts for normally off GaN-FETs were examined. A hybrid metal-oxide-semiconductor HFET structure is a promising candidate for obtaining devices with a lower on-resistance (Ron) and a high breakdown voltage (Vb).

High power AlGaN/GaN HFET with a high breakdown voltage of over 1.8 kV on 4 inch Si substrates and the suppression of current collapse

In this paper, we successfully demonstrate an AlGaN HFET with a high breakdown voltage of over 1.8 kV on 4 inch Si substrates. In order to obtain the high breakdown voltage and to improve the crystalline quality of GaN layers, a thick GaN epitaxial layer including a buffer layer with a total thickness of over 6 mum was grown. The breakdown voltage and the maximum drain current were achieved to be over 1.8 kV and 120 A, respectively. Furthermore, the suppression of the current collapse phenomenon is examined. The on-resistance is not so significantly increased up to the high drain off-bias-stress of 1.0 kV.

Over 1.7 kV normally-off GaN hybrid MOS-HFETs with a lower on-resistance on a Si substrate

In this study, normally-off GaN hybrid MOS-HFET devices on 4-inch Si substrates were fabricated, and the device characteristics were examined. As a result, the breakdown voltage (Vb) was improved using a combination of a high-resistive carbon-doped back barrier layer and a thin channel layer of 50 nm. The specific on-resistance (RonA) was estimated to be less than 7.1 mΩcm2 for Lgd = 12 μm, and Vb was estimated to be over 1.71 kV for Lgd = 18 μm. To our knowledge, these values are the best results ever reported for normally-off GaN-based MOSFETs.

Room temperature ethanol sensor based on ZnO prepared via laser ablation in water

The present work reports on room-temperature ethanol sensing performance of ZnO nanospheres and nanorods prepared using pulsed laser ablation in water. Nanosecond and millisecond lasers were used to prepare ZnO nanomaterials with hexagonal wurtzite crystal structure. The two contrasting nanostructures were tested as gas sensors towards volatile compounds such as ethanol, ammonia, and acetone. At room temperature, devices based on both ZnO nanomaterials demonstrated selectivity for ethanol vapor. The sensitivity of nanospheres was somewhat higher compared to that of nanorods, with response values of ~19 and ~14, respectively, towards 250 ppm. Concentrations as low as 50 ppm could be easily detected.

Novel Circuitry Configuration with Paired-Cell Erase Operation for High-Density 90-nm Embedded Resistive Random Access Memory

We propose a novel circuitry configuration for high-density 90-nm embedded resistive random access memory (ReRAM). The memory cells are operated at 2 V, and a small memory cell size of 6F2 consisting of a 1.2-V standard transistor and a resistive junction (1T–1R) is designed, where F is the feature size. The unique circuitry configuration is that each pair of source-lines connects to each source-line selective gate. Therefore, erasing is done by a pair of cells in turn in the whole sector, while the reading or programming is done by a random accessing operation. We simulated the ReRAM circuit for read and write operations with SPICE. As a result, we found that 5-ns high-speed read access was obtained in the 256-word lines (WLs) × 256-bit lines (BLs) and that the SET/RESET operation was stable.

Phase and Composition Control of Ni Fully Silicided Gates by Nitrogen Ion Implantation and Double Ni Silicidation

The phase and composition control of a Ni fully silicided (Ni-FUSI) gate electrode is investigated to achieve a wider process window for complementary metal–oxide–semiconductor (CMOS) device integration. We performed nitrogen ion implantation (N2 I/I) on polycrystalline silicon (poly-Si) prior to Ni deposition only for an n-MOS gate. The implanted nitrogen in the poly-Si layer suppresses the reaction of Ni and Si. As a consequence, the process temperature for Ni silicidation increased by ~20 °C compared with that in the case without implantation. It was also found that the grain size of the Ni silicide found in the N2 I/I-treated poly-Si layer is smaller, possibly due to nitrogen atoms bound to Si and/or cavities generated inside the poly-Si layer. We also propose double Ni silicidation for fabricating a p-MOS gate, where a Ni-rich silicide was formed by carrying out an additional Ni deposition and annealing on a Ni silicide film. The Ni-rich silicide was evaluated in terms of X-ray diffraction patterns and flat band voltage shifts on capacitance–voltage measurement. Combining these techniques will enable the development of an optimized process integration scheme for CMOS devices.

Investigation of Surface Pits Originating in Dislocations in AlGaN/GaN Epitaxial Layer Grown on Si Substrate with Buffer Layer

An AlGaN/GaN heterostructural layer with a crack-free smooth surface was grown on multiple buffer layers formed on a Si(111) substrate. On the AlGaN surface, pit arrays forming a network structure were observed by atomic force microscopy (AFM). In order to clarify the origin of these pit arrays, the AlGaN/GaN layer was investigated using transmission electron microscopy (TEM). As a result, similar network structures of threading edge dislocations in the AlGaN/GaN layer were observed by plan-view TEM. It was thus confirmed that the surface pit arrays observed by AFM represent the surface termination of edge dislocations formed at the small-angle boundaries of slightly misoriented crystal domains.

A Novel MTJ Shape with Large Write Operation Margin for High Density MRAM

We propose a novel MTJ shape, “Sandglass”, to have an excellent asteroid curve. A unique switching mechanism of the MTJ is confirmed by LLG simulation and experiment. The “Sandglass” MTJ improves not only the write disturbance issue but also a memory cell size to be a complete 8F. This has the potential to realize high density MRAM. Introduction Magnetoresistive Random Access Memory (MRAM) is one of the candidates for the low power SoC memory. This is because of not only non-volatility that makes electricity consumption low in the stand-by mode but its high capacity, high speed operation, unlimited read / write endurance, and CMOS process compatibility. The factors to achieve high density MRAM are to realize wide write operation margin to widen “0” and ”1” separation and eliminate the disturbance of half-selected cells during programming. Savtchenko switching mode was reported as an epoch-making invention to improve the write margin [1]. However, the large switching current [2] and its complicated write procedure is pointed out. On the other hand, a conventional switching mode with a designed magnetic tunnel junction (MTJ) shape, which is considered the magnetization to have an ideal asteroid, is effective to resolves the write disturbance issue, additionally including relatively low switching current and high thermal stability [3]. In this paper, we propose a novel MTJ shape that has an excellent asteroid curve and that forms an 8F unit memory cell. Concept of New MTJ Shape Our proposed MTJ shape is like a “Sandglass”. Fig.1 shows the shape of the 200nm x 200nm “Sandglass” MTJ and its magnetization configurations that are simulated by the Landau-Lifshitz-Gilbert (LLG) simulator. When magnetic field is applied from only a bit line in Fig.1 (c), the magnetization of the half-selected cells generates two C-state configurations in the upper and lower sides, respectively, in Fig.1 (a). In this case, the write disturbance of half-selected cells is improved greatly, because it is very hard to switch the magnetic orientation of the C-state free-layer. The non-selected cell also forms the same configuration of the half-selected cell. Meanwhile, magnetic field is applied from both a bit line and a write-word line, the magnetization of the selected cell changes into one continuous S-state configuration in Fig.1 (b). In general, the switching field of the S-state is lower than that of the C-state, the switching field of the selected cell, therefore, reduces drastically. Fig2 shows the schematic of the write operation margin in the asteroid characteristic. This type of the write operation margin is mainly determined by difference between the S-state curve and C-state one. Consequently, the larger difference of both curves generates the wider write operation margin. Thus the switching mechanism is unique and different from switching mode proposed by Toshiba [3] or Cypress [4]. Fig.3 shows that the calculated asteroid curves are little dependent on the both sides of the dent shape, as shown in Fig.4. It indicates that the large yield of memory cells is expected. Additionally, these memory cell arrays are designed as a complete minimum 8F par unit cell as shown in Fig.5. This is because the aspect ratio of the “Sandglass” MTJ is unity, though that of conventional MTJ shapes is twice or more. Experiment results We fabricated “Sandglass” MTJs. The MTJ stack consisted of Bottom-electrode/PtMn/CoFe/Ru/CoFe/AlOx/NiFe/CoFe/Top -electrode. Fig.6 shows the cross-sectional view of TEM image. Measured asteroid curves of both “Sandglass” MTJ of 260nm x 400nm and the conventional elliptic MTJ of 200nm x 400nm are shown in Fig.7. The excellent asteroid of the “Sandglass” MTJ is confirmed that the write operation margin is much larger and the switching field is lower than that of the elliptic one. Fig.8 shows the R-H curve of the “Sandglass” MTJ. It is different from that of the conventional MTJ shape but the typical behavior to change the magnetization of between C-state and S-state distinctly. Conclusion We proposed a novel MTJ shape, the “Sandglass”, to improve both the write disturbance issue using with a new switching concept and to have a potential to design a complete minimum 8F. An excellent asteroid with the large write operation margin was confirmed by LLG simulation and experiment. We found that the “Sandglass” MTJ was the most appropriate for high density MRAM. Acknowledgement The authors would like to thank Y. Yamazaki, T. Nagata, H. Noshiro, S. Umehara and M. Sato for their support of this work. References [1]M. Durlam, et al., ”A 0.18μm 4Mb Toggling MRAM”, IEDM Tech.Dig., pp995-997, 2003. [2]M. motoyoshi, el al., “A study for 0.18μm High-Density MRAM”, Symp. on VLSI Tech. Dig., pp.22-23, 2004. [3]T. Kai, et al., ”Improvement of robustness against write disturbance by novel cell design for high density MRAM”, IEDM Tech. Dig., pp583-586 2004. [4]K. Ounadjela, et al., “Write Data Issues For Making Functional 256kb MRAM Parts”, 9th Joint MMM/Intermag Conference, GE-01, 2004. Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials, Kobe, 2005, -1042H-9-2 pp.1042-1043

Phase and Composition Control of Ni-FUSI gates by N2 I/I with Double Ni-silicidation

It has been an urgent challenge to introduce high-k gate dielectrics and metal gates into practical applications. In particular, Ni-fully silicided (Ni-FUSI) gate is attractive replacement for poly-Si due to fundamental limitations of poly-Si/metal oxide stack like Fermi-level pinning effect and consistency to conventional poly-Si process flow [1]. In the FUSI process, phase and composition of Ni-silicide are key factors to control appropriate effective work function, where suitable phases for nand p-MOS correspond to Si-rich (NiSi2, and NiSi) and Ni-rich silicide (Ni2Si, Ni31Si12 and Ni3Si), respectively [2]. Poly-Si etch back process combined with 2 step annealing is well known CMOS integration scheme [3]. Thinner poly-Si thickness for pMOS (higher thickness ratio of Ni to Si) than that for nMOS makes it Ni-rich silicide with larger work function. However, this technique has considerably difficult controllability for Ni-silicide phases on the CMOS process, because the optimal condition for n-MOS is slightly overlapped with that for p-MOS. To overcome this difficulty, limited and enhanced silicidation techniques are required for nand p-MOS, respectively, to widen their process window. In this paper, we investigate nitrogen (N2) implantation into poly-Si prior to Ni-silicidation for nMOS and an additional Ni deposition and annealing (double Ni-silicidation process) for pMOS.

A Novel Magnetic Tunneling Junction Shaped Cell with Large Write Operation Margin for High-Density Magnetoresistive Random Access Memory

Magnetoresistive random access memory (MRAM) is one of several candidates for low-power and high-density system-on-chip (SoC) memory. In this paper, we propose a novel magnetic tunneling junction (MTJ) shape, called the sandglass (or hourglass), that has both an excellent asteroid curve for preventing write disturbance and a minimum memory of 8F2, where F is the feature size. A unique magnetic switching mechanism that works under decreasing magnetic switching field was compared with that of conventional MTJs simulated using the Landau–Lifshitz–Gilbert (LLG) simulator. We fabricated both a sandglass MTJ of 260×420 nm2 and a conventional elliptic MTJ of 200×400 nm2. The excellent asteroid curve of the sandglass MTJ is confirmed which exhibits both a larger write operation margin and a 50% lower switching field than those of the conventional elliptic MTJ. The sandglass MTJ cell is a promising candidate for realizing high-density MRAM.