Yoshinao Miura

High performance superjunction UMOSFETs with split p-columns fabricated by multi-ion-implantations

We propose superjunction UMOSFET devices (SJ-UMOS) with split p-column structures for automotive applications with rated voltage of 40-75 V. The split p-column fabricated by multi-ion-implantations consists of p-type islands separated by small distances in an n-type epi-layer. This structure was designed to improve the repetitive inductive switching performance without sacrificing the original benefits of the SJ structure. We achieved a specific on-resistance of 28.7 m/spl Omega/mm/sup 2/ at a gate voltage of 10 V for breakdown voltage of 68.0 V. In addition, we confirmed high immunity against inductive switching stress at 175/spl deg/C and good reverse recovery properties.

Enhancement-mode GaN-on-Si MOS-FET using Au-free Si process and its operation in PFC system with high-efficiency

We have developed an enhancement-mode GaN-on-Si MOS-FET with a thin GaN channel (40nm) on a thick AlGaN back barrier layer (1um), using Au-free 150-mm Si process. The developed device showed a threshold voltage Vt of 1.1 V, an on-resistance Ron of 5.4 mΩcm2 and a breakdown voltage BV of 730 V. The developed E-mode GaN MOS-FETs demonstrated the potential for compact and efficient power electronics. A Power Factor Correction (PFC) circuit using the packaged GaN device (20A, 650V) operated with high efficiency of > 94 % at Pout=300 W, Vout=390 V and fSW=300 kHz.