Kenya Kobayashi

High voltage SOI CMOS IC technology for driving plasma display panels

We have developed a new high voltage CMOS (HV-CMOS) IC technology by using 5 /spl mu/m-thick SOI. In this technology, trench isolation and a 0.5 /spl mu/m rule CMOS process are also adopted. We have examined seven series HV-CMOS fabrication processes in different voltage ratings (in which the maximum voltage rating was 250 V) and optimized their characteristics respectively. The HV-CMOS IC with full-CMOS type level shifter is suited to low power consumption color plasma display panels (C-PDPs) and high-speed switching has been confirmed. The chip size of the developed PDP scan driver IC could be reduced by 40% compared with the conventional chip.

High performance superjunction UMOSFETs with split p-columns fabricated by multi-ion-implantations

We propose superjunction UMOSFET devices (SJ-UMOS) with split p-column structures for automotive applications with rated voltage of 40-75 V. The split p-column fabricated by multi-ion-implantations consists of p-type islands separated by small distances in an n-type epi-layer. This structure was designed to improve the repetitive inductive switching performance without sacrificing the original benefits of the SJ structure. We achieved a specific on-resistance of 28.7 m/spl Omega/mm/sup 2/ at a gate voltage of 10 V for breakdown voltage of 68.0 V. In addition, we confirmed high immunity against inductive switching stress at 175/spl deg/C and good reverse recovery properties.

A 5 to 130 V level shifter composed of thin gate oxide dual terminal drain PMOSFETS

The market demand for high performance and cost effective flat panel display (FPD: e.g. plasma display, electroluminescent display) system has mandated that FPD driver designs need to be more cost effective. The driver plays a vital role in determining the FPD (system) performance and manufacturing cost as well as the panel itself. The driver is basically a device which can translate digital data signals (typically 5 V-logic) to the series of high voltage outputs (60 to 300 V) for the panel electrode load array. To reduce the manufacturing cost, this paper describes a study of the novel 5 to 130 V level shifter with Dual Terminal Drain PMOSFETs (DTDPMOS) for the first time. To adopt this level shifter, although the driver IC consists of both high and low voltage CMOS, the high voltage CMOS can be realized with the same thin gate oxide as the low voltage CMOS.

An intelligent power device using poly-Si sandwiched wafer bonding technique

A new simple isolation structure has been realized by using poly-Si sandwiched wafer bonding technique. We confirmed that the poly-Si layer enabled the bonded interface to be void-free and electrically perfect, and had the effect that it enabled the reverse recovery time of the parasitic diode of Vertical DMOSFET (VDMOS) to be short. In the new structure, the isolation capabilities were adequate to integrate 60 V VDMOS and control circuits on the same chip. Especially, the parasitic bipolar action has been suppressed. We evaluated an intelligent power device which uses this technique and have confirmed the availability of the new isolation structure.

Ultralow on-resistance 30–40 V UMOSFET by 2-D scaling of ion-implanted superjunction structure

We present an ultimately narrow pitch superjunction UMOSFET (SJ-UMOS) with a record low specific on-resistance (Rsp) for automotive applications. This high performance device was designed by not only shrinkage of lateral p/n pitch, but reduction of longitudinal dimension for voltage sustaining region including ion-implanted p-columns. The refined technologies brought us a fully depleted SJ structure with extremely scaled pitch to a minimum of 1.0 μm. In the developed SJ-UMOS, an ultralow Rsp (VGS = 10 V) of 4.75 miimm2 (2.95 miimm2 without a substrate component) at a breakdown voltage of 32.8 V was obtained. We also confirmed excellent properties of low RonQG FOM and soft recovery operation of a body diode due to the best architecture around the gate electrode of the MOSFET.

Sub-micron Cell Pitch 30 V N-channel UMOSFET with Ultra Low On-resistance

We developed new sub-micron cell pitch 30 V n-channel UMOSFET with ultra low on-resistance. In the UMOSFET structure, we adopted a layered oxide as interlayer dielectric and equalized the width to the trench gate width to realize the narrow unit cell pitch (<1.0 mum). We optimized layout dimensions for new rectangular cell design and stripe design. As a result, we achieved the lowest specific on-resistance (Rsp) of 4.3 mOmegamm2 at Vgs=10 V and 5.0 mOmegamm2 at Vgs=4.5 V in 30 V class for the fabricated rectangular cell UMOSFET.

Application of partially bonded SOI structure to an intelligent power device having vertical DMOSFET

In recent years, many types of Intelligent Power Devices (IPDs) have been developed. A key technology of developing the IPDs is the isolation between power device and control circuit. The isolation structures and its manufacturing methods are required to be more efficient and cost effective. We had been developed a low side switch IPD having Vertical DMOSFET (VDMOS) output by using poly-crystalline silicon sandwiched wafer bonding (PSB) technique. In this PSB structure, it is easy to achieve void-free bonding because the extremely flat poly-crystalline silicon (poly-Si) layer surface and the single-crystalline silicon (Si) substrate surface are bonded together. However, the PSB structure is still expensive. To reduce the fabrication cost, we have made a study of the direct bonding without poly-Si and proposed a new SOI structure named partially bonded (PB) structure. This paper reports the evaluation results that we applied the PB structure to a low side switch IPD for the first time.

Void-Free Bonded SOI Substrates for High-Voltage, High-Current Vertical DMOS-Type Power ICs

New isolated structures for intelligent power ICs were developed using a wafer bonding technique. These structures have partial buried oxide films for dielectric isolation and buried poly-Si layers for wafer bonding. In this bonding technique, bonding surfaces are a poly-Si layer and a crystalline silicon surface; this combination of bonding surfaces leads to void-free bonding. The electrical perfection of the vertical output device in the new structure was obtained by diffusing antimony into the poly-Si layer. These results indicate that intelligent power ICs can be manufactured by using the new structure.