Yoshinori Kusuda

Auto Correction Feedback for ripple suppression in a chopper amplifier

This paper proposes a local feedback, named Auto Correction Feedback (ACFB), used in a chopper amplifier to suppress its offset related ripple. It nulls out amplifiers offset in DC domain which would otherwise become modulated ripple at the chopper amplifiers output, instead of filtering the ripple by a post filter. The proposed chopper amplifier with the ACFB achieves 45dB ripple attenuation without introducing noise penalty, which has been proved by both simulation and measurement.

A 60 V Auto-Zero and Chopper Operational Amplifier With 800 kHz Interleaved Clocks and Input Bias Current Trimming

An auto-zero and chopper operational amplifier with a 4.5-60 V supply voltage range is realized, using a 0.18 μm CMOS process augmented by 5 V CMOS and 60 V DMOS transistors. It achieves a maximum offset voltage drift of 0.02 μV/°C, a minimum CMRR of 145 dB, a noise PSD of 6.8 nV/√Hz, and a 3.1 MHz unity gain bandwidth, while dissipating 840 μA of current. Up-modulated chopper ripple is suppressed by auto- zeroing. Furthermore, glitches from the charge injection of the input switches are mitigated by employing six parallel input stages with 800 kHz interleaved clocks. This moves the majority of the glitch energy up to 4.8 MHz, while leaving little energy at 800 kHz. As a result, the requirements on an external low-pass glitch filter is relaxed, and a wider usable signal bandwidth can be obtained. Maximum input bias current due to charge injection mismatch is reduced from 1.5 nA to 150 pA by post production trimming with an on-chip charge mismatch compensation circuit.

A 5.9nV/√Hz chopper operational amplifier with 0.78μV maximum offset and 28.3nV/°C offset drift

Many auto-zero or chopper operational amplifiers have been reported with low offset and low-offset drift. The resulting baseband noise can also be a significant error source, and thus reducing the total error down to sub μV levels at DC and low frequencies has been targeted. Chopping is more suitable to lower the baseband noise PSD, as it is primarily determined by the broad-band thermal noise floor and not aliased by the high frequency noise [1]. Reducing the thermal noise floor requires higher value of input transconductance [1]. Consequently, more capacitance or higher output transconductance is required to stabilize the overall feedback loop with regular Miller compensation. A 6.5nV/√Hz conditionally stable chopper operational amplifier has been reported, using multi-pole feedforward compensation techniques [2]. Unconditionally stable chopper operational amplifiers presented so far exhibit more than 10nV/√Hz noise PSD [1,3–5]. This paper reports a 5.9nV/√Hz unconditionally stable chopper operational amplifier with 1.47mA supply current and 1.26mm2 die area, achieved by phase compensation using current attenuation. In addition, adaptive clock level shift and backgate biasing for the input chopping allows optimization for noise and offset, realizing 0.78μV maximum offset with a worst-case 28.3nV/°C drift.

A 5.6 nV/ √Hz Chopper Operational Amplifier Achieving a 0.5 μV Maximum Offset Over Rail-to-Rail Input Range With Adaptive Clock Boosting Technique.

This paper presents a standalone 5.6 nV/√Hz chopper op-amp that operates from a 2.1-5.5 V supply. Frequency compensation is achieved in a power-and area-efficient manner by using a current attenuator and a dummy differential output. As a result, the overall op-amp only consumes 1.4 mA supply current and 1.26 mm2 die area. Up-modulated chopper ripple is suppressed by a local feedback technique, called auto correction feedback (ACFB). The charge injection of the input chopping switches can cause residual offset voltages, especially with the wider switches needed to reduce thermal noise. By employing an adaptive clock boosting technique with NMOS input switches, the amount of charge injection is minimized and kept constant as the input common-mode voltage changes. This results in a 0.5 μV maximum offset and 0.015 μV/°C maximum drift over the amplifiers entire rail-to-rail input common-mode range and from -40 °C to 125 °C. The design is implemented in a 0.35 μm CMOS process augmented by 5 V CMOS transistors.

5.1 A 60V auto-zero and chopper operational amplifier with 800kHz interleaved clocks and input bias-current trimming

Precision operational amplifiers (opamp) with 30V supply operation have been widely used to support industrial, instrumentation, and other applications [1]. Most of them have been realized with BJT or JFET processes [1] to offer voltage noise PSD better than 10nV/√Hz and offset voltage drift better than 1μV/°C. Recently, opamps with similar specifications have become available using CMOS based processes [2-4], which can offer a cheaper wafer price. Auto-zeroing and/or chopping are used as essential techniques to reduce offset voltage drift and 1/f noise associated with CMOS input differential pairs. The switching action of those techniques, however, results in unwanted output ripples and glitches, which requires a post-filter and limits usable signal bandwidth. Increasing the switching frequency can extend the usable signal bandwidth, though it introduces DC errors such as offset voltage drift and input bias current. Maximum offset voltage drift of 0.02μV/°C and an input bias current of 600pA have been achieved [3], although the switching frequency at 60kHz limits the usable signal bandwidth. A high switching frequency of 333kHz has been achieved [2], while the maximum offset voltage drift and input bias current are 0.085μV/°C and 850pA, respectively.