Michael Coln

Split ADC architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC

For original article by J. McNeill et al. see ibid., vol.40, no.12, p.2437-45, Dec. 2005.

All-Digital Background Calibration of a Successive Approximation ADC Using the “Split ADC” Architecture

The “split ADC” architecture enables fully digital calibration and correction of nonlinearity errors due to capacitor mismatch in a successive approximation (SAR) ADC. The die area of a single ADC design is split into two independent halves, each converting the same input signal. Total area and power is unchanged, resulting in minimal increase in analog complexity. For each conversion, the half-sized ADCs generate two independent outputs which are digitally corrected using estimates of capacitor mismatch errors for each ADC. The ADC outputs are averaged to produce the ADC output code. The difference of the two outputs is used in a background calibration algorithm which estimates the error in the correction parameters. Any nonzero difference drives an LMS feedback loop toward zero difference which can only occur when the average error in each correction parameter is zero. A novel segmentation and shuffling scheme in the SAR capacitive DAC enables background calibration for a wide range of input signals including dc. Simulation of a 16 bit 1 Msps SAR ADC in 180 nm CMOS shows calibration convergence within 200 000 samples.

“Split ADC” Calibration for All-Digital Correction of Time-Interleaved ADC Errors

The ldquosplit analog-to-digital converter (ADC)rdquo architecture enables fully digital calibration and correction of offset, gain, and aperture-delay mismatch errors in time-interleaved ADCs. The calibration of M interleaved ADCs requires 2M + 1 half-sized ADCs, a minimal increase in analog complexity. Each conversion is performed by a pair of half-sized ADCs, generating two independent outputs that are digitally corrected using estimates of offset, gain, and aperture-delay errors. The ADC outputs are averaged to produce the ADC output code. The difference of the outputs is used in a calibration algorithm that estimates the error in the correction parameters. Any nonzero difference drives a least-mean-square feedback loop toward zero difference, which can only occur when the average error in each correction parameter is zero. A simulation of a 4 : 1-time-interleaved 16-bit 12-MSps successive-approximation-register ADC shows calibration convergence within 400 000 samples.

Digital Background-Calibration Algorithm for “Split ADC” Architecture

The ldquosplit ADCrdquo architecture enables continuous digital background calibration by splitting the die area of a single ADC design into two independent halves, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for a background-calibration algorithm. Since both ADCs convert the same input, when correctly calibrated, their outputs should be equal, and the difference should be zero. Any nonzero difference provides information to an error-estimation algorithm, which adjusts digital-calibration parameters in an adaptive process similar to a least mean square algorithm. This paper describes the calibration algorithm implemented in the specific realization of a 16-bit 1-MS/s algorithmic cyclic ADC. In addition to correcting ADC linearity, the calibration and estimation algorithms are tolerant of offset error and remove linear scale-factor-error mismatch between the ADC channels. Simulated results are presented confirming self-calibration in approximately 10 000 conversions, which represents an improvement of four orders of magnitude over previous statistically based calibration algorithms.

A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability

This paper presents a 20b clockless DAC designed for precision calibrated systems. The architecture is a 6b parallel resistor voltage divider with a 14b R-2R subDAC. This architecture is inherently good for noise and temperature stability. Major causes of nonlinearity are discussed. A single current-output calibration DAC corrects for both random resistor mismatch and systematic resistor nonlinearity. A force and sense switch topology overcomes INL from CMOS switch resistance. The DAC is implemented in a 0.6 μm 30 V BiCMOS process with 5 V CMOS devices and Si-Cr thin-film resistors. It achieves 0.33 ppm INL and 7.5 nV/√Hz noise with a ±10 V output span. It has 0.05 ppm/°C temperature stability and settles in 1 μs. Current consumption is 4.2 mA from 30 V supplies, excluding power required for external reference buffers.

A 16-bit 16MS/s SAR ADC with on-chip calibration in 55nm CMOS

This paper presents a SAR ADC that is much smaller and faster than the recently reported precision (16-bit and beyond) SAR ADCs [1, 2, 3]. In addition, it features low input capacitance and an efficient on-chip foreground calibration algorithm to fix bit weight errors. Several other enabling techniques are also used, including signal independent reference switching using reservoir capacitors to improve speed and reduce area, LSB repeats and ADC residue measurement to improve efficiency. The prototype achieves 97.5dB SFDR while operating at 16MS/s and consumes 16.3mW. It was fabricated in 55nm CMOS and occupies 0.55mm2.

A 20b clockless DAC with sub-ppm-linearity 7.5nV/vHz-noise and 0.05ppm/°C-stability

DACs without continuous clocking are often favored in applications such as medical imaging and scientific instrumentation. The DACs in these high-precision systems are commonly endpoint-calibrated. After this calibration, a non-ideal DAC contributes three main sources of error: noise, temperature drift, and INL. The segmented voltage-mode R-2R DAC is an attractive architecture for reducing the first two of these error sources. Resistor Johnson noise is fixed by the DACs code-independent output resistance, which is readily lowered by the combination of several parallel segments. The complete signal path can be built using opamps that have a minimal noise gain of unity. This architecture also benefits from inherently zero endpoint error, avoiding any gain or offset drift over temperature. However, this preferred architecture for noise and temperature drift suffers from several sources of INL including: resistor mismatch, voltage losses across CMOS switches, and the nonlinearity of each resistor.

A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS

This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) that is much smaller and faster than other recently reported precision (16-bit and beyond) SAR ADCs. In addition, it features low input capacitance and an efficient on-chip foreground calibration algorithm to fix bit weight errors. Several other enabling techniques are also used, including signal independent reference using reservoir capacitors to improve speed and reduce area, plus LSB repeats and statistical residue measurement to improve efficiency. The prototype achieves 97.5-dB spurious-free dynamic range at 100-kHz input while operating at 16 MS/s and consumes 16.3 mW. It was fabricated in a 55-nm CMOS process and occupies 0.55 mm2.

A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS

This paper presents a first reported passive-charge-sharing SAR ADC that achieves 16 bit linearity. It is known that on chip passive-charge-sharing suffers from poor linearity due to the unregulated reference voltage during bit trials. The proposed unique ADC architecture and calibration technique addresses the issue of signal dependent reference voltage droop during SAR ADC bit trials and orthogonalize the bit weights to achieve 16bit linearity. In addition, the proposed architecture maximizes SNR by sampling on to the bit cap, the first reported in this type of SAR ADC. Measurement result from a prototype test chip shows +/−0.8 LSB (16-bit level) INL at 1MSPS.

Split ADC background self-calibration of a 16-b successive approximation ADC in 180nm CMOS

A 16-b, 1MSps successive approximation ADC in 180nm CMOS uses the ”split ADC” architecture to enable continuous, all-digital, background self-calibration of ADC linearity. Convergence of calibration parameters to noise-limited accuracy is demonstrated with an adaptation time constant less than 300ms. In the capacitive DAC, a novel segmentation and shuffling approach is used to mitigate requirements on input signal activity; calibration is possible even in the presence of DC input signals.