Yoshitada Iyama

L-band internally matched Si-MMIC front-end

A 1.9 GHz-band internally matched Si-MMIC front-end, fabricated in standard 0.8 /spl mu/m BiCMOS process, was developed. This IC front-end contains a MOSFET T/R switch, a two-stage BJT low noise amplifier (LNA), and a down converter BJT mixer. Since the circuits are monolithically integrated on a low resistivity Si substrate, the coplanar waveguide (CPW) type spiral inductors are used to reduce the dielectric loss of on-chip matching circuits. The T/R switch has measured insertion loss of 2.5 dB and isolation of 25.5 dB at 0/3 V control voltage. The two-stage LNA has gain of 17.1 dB and noise figure (NF) of 2.9 dB at 2 V, 4 mA dc supply. The mixer has conversion gain of 5.9 dB and NF of 15 dB at 2 V, 1.7 mA dc supply. The measured performance of the fabricated Si-MMIC front-end indicates the possibility of application to mobile communication handset terminals.

X-band MMIC power amplifier with an on-chip temperature compensation circuit

An X-band MMIC power amplifier with an on-chip temperature compensation circuit has been presented. The temperature compensation circuit is composed of a diode and a resistor. The compensation circuit is applied to a 4 stage X-band MMIC power amplifier. The gain variation is improved from 5.5 dB to 1.3 dB in the temperature range between -10 degC and +80 degC.

High-isolation series-shunt FET SPDT switch with a capacitor canceling FET parasitic inductance

A novel series-shunt FET narrow-band high-isolation single-pole double-throw switch, which employs series capacitors to cancel the parasitic inductances has been developed. The proposed switch can have significantly high isolation characteristics at higher frequency. The fabricated two switches have demonstrated high isolation characteristics of 28.9 dB in the 28- and 18-GHz band, respectively.

X-band MMIC power amplifier with an on-chip temperature-compensation circuit

An X-band MMIC power amplifier with an on-chip temperature compensation circuit has been presented. The temperature compensation circuit is composed of a diode and a resistor. The compensation circuit is applied to a 4 stage X-band MMIC power amplifier. The gain variation is improved from 5.5 dB to 1.3 dB in the temperature range between -10 degC and +80 degC.

Transfer characteristic of IM/sub 3/ relative phase for a GaAs FET amplifier

Measured transfer characteristic of relative phase of the third order intermodulation distortion (IM/sub 3/) of a GaAs FET amplifier is described. The measurement system and method are also described. For drives in the weakly nonlinear region, the measured relative phase of IM/sub 3/ is equal to that of carriers, and agrees with the analysis result based on Volterra-series representation. For drives in the saturation region, the measured relative phase of IM/sub 3/ versus the input power is larger than that of carriers relative phase. The measured results and the measurement method are useful for the design and adjustment of predistortion type linearizer for GaAs FET high power amplifiers.

1.9 GHz/5.8 GHz-band on-chip matching Si-MMIC low noise amplifiers fabricated on high resistive Si substrate

The use of high resistivity Si substrates, instead of the conventional low resistivity Si substrate, enables one to reduce the loss of spiral inductor for the on-chip matching circuit by 61% at 1.9 GHz and by 78% at 5.8 GHz and to improve gain and noise performance of the BJT. These improvements are explained as the reduction of dielectric loss of substrate by referring to equivalent circuit model extraction. The fabricated 1.9 GHz-band on-chip matching LNA performs 13.4 dB gain, 1.9 dB NF with 2 V, 2 mA DC power and 5.8 GHz-band LNA performs 6.9 dB gain, 3.3 dB NF with 3 V, 3 mA DC power.The use of high resistive Si substrate, instead of conventional low resistive Si substrate, enables one to reduce the loss of spiral inductor for on-chip matching circuit by 61% at 1.9 GHz and by 78% at 5.8 GHz, and to improve gain and noise performance of the BJT. These improvements are explained as the reduction of dielectric loss of substrate by referring to equivalent circuit model extraction. The fabricated 1.9 GHz-band on-chip matching LNA performs 13.4 dB gain, 1.9 db NF with 2 V, 2mA d.c. power and 5.8 GHz-band LNA performs 6.9 dB gain, 3.3 dB NF with 3 V, 3 mA d.c, power.

A 1.9GHz Even Harmonic Type Direct Conversion Si-MMIC Receiver

A direct conversion Si-MMIC receiver, which consists of an on-chip matching LNA and a pair of even harmonic type SBD mixers including base band top amplifier, is developed. These circuits are integrated on high resistive Si substrates by using BiCMOS process. The receiver performs NF of 3.5 dB, conversion gain of 28.0 dB and IIP2 of ¿7 dBm with 3 V / 11.5 mA d.c. power and ¿3 dBm of local power. This results shows the feasibility to implement Si-MMIC direct converter for wireless handset use.

A 6-18 GHz 20 W SPDT switch using shunt discrete PIN diodes

A broadband high power SPDT switch using shunt discrete PIN diodes is presented. By using shunt SPDT switch configuration, high power performance can be obtained. A novel structure, in which matching sections are added outside of shunt PIN diodes, provides broadband characteristics. The insertion loss of the fabricated MIC switch is less than 2.0 dB at 6 to 18 GHz, and is less than 1.5 dB at 7 to 17 GHz. The power handling capability is over 20 W CW at 12 GHz.

L-band internally matched Si-MMIC low noise amplifier

A Si-MMIC low noise amplifier (LNA), fabricated in conventional 0.8 /spl mu/m Bi-CMOS process, was developed. This LNA is monolithically integrated on a low resistive Si substrate with coplanar waveguide (CPW) type matching circuits. At 1.9 GHz, noise figure of 2.7 dB and gain of 10 dB were obtained at 2 V/2 mA d.c. supply.

A Ku-Band Matched Embedded-FET Phase Shifter

A Ku-band matched embedded-FET phase shifter achieving compact and low insertion loss performance is described. It consists of only a few circuit elements of a series embedded-FET incorporated with a high impedance line and an inductive matching network switched by an SPST switch. A six-bit phase shifter has been developed, consisting of these matched embedded-FET phase shifters for lower bit sections (22.5 °, 11.25 °, 5.625°) and high pass / low pass type phase shifters [1]-[2] for higher bit sections. It has a small size and a low insertion loss.