Shunji Kubo

L-band internally matched Si-MMIC front-end

A 1.9 GHz-band internally matched Si-MMIC front-end, fabricated in standard 0.8 /spl mu/m BiCMOS process, was developed. This IC front-end contains a MOSFET T/R switch, a two-stage BJT low noise amplifier (LNA), and a down converter BJT mixer. Since the circuits are monolithically integrated on a low resistivity Si substrate, the coplanar waveguide (CPW) type spiral inductors are used to reduce the dielectric loss of on-chip matching circuits. The T/R switch has measured insertion loss of 2.5 dB and isolation of 25.5 dB at 0/3 V control voltage. The two-stage LNA has gain of 17.1 dB and noise figure (NF) of 2.9 dB at 2 V, 4 mA dc supply. The mixer has conversion gain of 5.9 dB and NF of 15 dB at 2 V, 1.7 mA dc supply. The measured performance of the fabricated Si-MMIC front-end indicates the possibility of application to mobile communication handset terminals.

A high performance CBiCMOS with novel self-aligned vertical PNP transistors

This paper describes a vertical PNP transistor with a novel self-aligned structure and a complementary BiCMOS process which makes use of it. The PNPs emitter electrode is formed at the same fabrication step as that of a self-aligned NPNs base electrode, and the base electrode is formed at the same fabrication step as that of the self-aligned NPNs emitter electrode. The PNPs have been fabricated adding only one photo-mask and one doping step to the BiCMOS processes. The maximum cutoff frequency or PNP and NPN transistors are 4.2 GHz and 20 GHz, respectively. The MOS transistors are compatible with simple CMOS devices.

0.8 /spl mu/m BiCMOS process with high resistivity substrate for L-band Si-MMIC applications

This paper describes a BiCMOS process for L-band Si-MMIC applications. Low loss transmission line, high performance bipolar transistor (emitter minimum size /spl sim/0.5 /spl mu/m), 0.8 /spl mu/m CMOS, and Schottky diode are integrated on a high resistivity silicon substrate (HRS). Losses of two types of transmission lines, which are composed of multilevel metal layers, are investigated in both high and low resistivity substrates. A low noise amplifier (LNA) is fabricated on a conventional low resistivity silicon substrate.

1.9 GHz/5.8 GHz-band on-chip matching Si-MMIC low noise amplifiers fabricated on high resistive Si substrate

The use of high resistivity Si substrates, instead of the conventional low resistivity Si substrate, enables one to reduce the loss of spiral inductor for the on-chip matching circuit by 61% at 1.9 GHz and by 78% at 5.8 GHz and to improve gain and noise performance of the BJT. These improvements are explained as the reduction of dielectric loss of substrate by referring to equivalent circuit model extraction. The fabricated 1.9 GHz-band on-chip matching LNA performs 13.4 dB gain, 1.9 dB NF with 2 V, 2 mA DC power and 5.8 GHz-band LNA performs 6.9 dB gain, 3.3 dB NF with 3 V, 3 mA DC power.The use of high resistive Si substrate, instead of conventional low resistive Si substrate, enables one to reduce the loss of spiral inductor for on-chip matching circuit by 61% at 1.9 GHz and by 78% at 5.8 GHz, and to improve gain and noise performance of the BJT. These improvements are explained as the reduction of dielectric loss of substrate by referring to equivalent circuit model extraction. The fabricated 1.9 GHz-band on-chip matching LNA performs 13.4 dB gain, 1.9 db NF with 2 V, 2mA d.c. power and 5.8 GHz-band LNA performs 6.9 dB gain, 3.3 dB NF with 3 V, 3 mA d.c, power.

A 1.9GHz Even Harmonic Type Direct Conversion Si-MMIC Receiver

A direct conversion Si-MMIC receiver, which consists of an on-chip matching LNA and a pair of even harmonic type SBD mixers including base band top amplifier, is developed. These circuits are integrated on high resistive Si substrates by using BiCMOS process. The receiver performs NF of 3.5 dB, conversion gain of 28.0 dB and IIP2 of ¿7 dBm with 3 V / 11.5 mA d.c. power and ¿3 dBm of local power. This results shows the feasibility to implement Si-MMIC direct converter for wireless handset use.

L-band internally matched Si-MMIC low noise amplifier

A Si-MMIC low noise amplifier (LNA), fabricated in conventional 0.8 /spl mu/m Bi-CMOS process, was developed. This LNA is monolithically integrated on a low resistive Si substrate with coplanar waveguide (CPW) type matching circuits. At 1.9 GHz, noise figure of 2.7 dB and gain of 10 dB were obtained at 2 V/2 mA d.c. supply.

3. Ogb/s, 272mw, 8:1 Multiplexer And 4.1gb/s, 388mw, 1:8 Demultiplexer

I . INTRODUCTION Optical transmission systems require multiplexer and demultiplexer chips as the major ingredients. There have been proposed and realized several architectures for multiplexers and demultiplexers. Such as the shift resister architecture, the interleaved architecture, the series gated architecture, and so on. In general, these previous architectures have aimed at high speed operation rather than low power dissipation. In multiplexers, the series gated architecture is effective in reducing power dissipation because the series gate can implement complex logic with fewer current sources. However, the architecture requires the 3-level for the series gate [l]. Thus it is difficult to lower the supply voltage for multiplexers. Furthermore, the architecture requires larger current to drive the 3-level series gate at high speed. On the other hand, the interleaved architecture is widely used in demultiplexers. In this architecture, conversion from serial to parallel data requires the lst, 2nd and 3rd stage flipflops [2]. This requires a large amount of hardware and therefore consumes much power. In this paper, 8:l multiplexer and 1% demultiplexer chips with low power dissipation are described. The multiplexer chip adopts the modified series gated architecture, while the demultiplexer chip adopts the modified interleaved architecture.

L-band internally matched front-end Si-MMIC

A 1.9GHz-band front-end Si-MMIC was developed, which includes MOSFET T/R switch, two-stage BJT low noise amplifier (LNA), and down converter BJT mixer. This front-end IC is monolithically integrated on a low resistive Si substrate with coplanar waveguide (CPW) type matching circuits in standard 0.8¿m BR-CMOS process. The T/R switch of the front-end has the measured insertion loss of 2.5dB and isolation of 25.5dB at 0 / 3V control voltage. The LNA has gain of 17.1dB and noise figure (NF) of 2.9dB at 2V, 4mA d.c. supply. The mixer has conversion gain of 5.9dB and NE of l5dB at 2V, 1.7mA d.c. supply. The measured performance of this frontend IC indicates the possibility of application for mobile communication handset terminals.

800 MHz-band low noise low distortion Si-MMIC front-end using BJT/MOSFET LNA and MOSFET mixer

Both low noise and low distortion characteristics are strongly desired for cellular terminal receiver application. In the case of Si-MMIC, BJT has superior feature in its low noise performance and MOSFET has it in low distortion performance. By using BJT amplifier as the 1st stage of LNA and MOSFET as the 2nd stage of LNA and a down mixer, both low noise and low distortion performance is achieved. The fabricated Si-MMIC front-end, which contains two-stage LNA and down mixer and LO amplifier, performs 3.7 dB NF, 16.7 dB conversion gain and -15.5 dBm IIP/sub 3/ with 3V/13.7 mA d.c. power and -10 dBm LO power.