Yoshitaka Sasago

The Impact of Random Telegraph Signals on the Scaling of Multilevel Flash Memories

This paper describes for the first time the observation of the threshold voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory. We acquired large-scale data of Vth fluctuation and confirm the existence of the tail bits generated by RTS. The amount of Vth broadening due to the tail bits becomes larger as the scaling advances, and reaches to more than 0.3 V in 45-nm node. Thus the RTS becomes prominent issue for the design of multilevel flash memory in 45-nm node and beyond

Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node

Threshold-voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory was observed for the first time. A large amount of data of Vth fluctuation was acquired by using a 90-nm-node memory array, and it was confirmed that a few memory cells have large RTS fluctuation exceeding 0.2 V. It was found that program-and-erase cycles increase Vth amplitude in a flash memory. It was also found by simulation and measurement that tail-bits are generated due to RTS in multilevel flash operation. The amount of Vth broadening due to the tail-bits was estimated to become larger as the scaling of memory cells advances and reaches more than 0.3 V in the 45-nm node. These results thus demonstrate that RTS will become a prominent issue in designing multilevel flash memory in the 45-nm node and beyond.

90-nm-node multi-level AG-AND type flash memory with cell size of true 2 F/sup 2//bit and programming throughput of 10 MB/s

The first true 2-F/sup 2//bit flash cell with a programming throughput of 10 MB/s was developed. In this cell, diffusion-layer local bit lines of an assist-gate AND-type flash are replaced by inversion-layer ones under assist gates. The bit-line pitch is thus reduced to 2 F. A drain-disturbance-free and soft-write-free flash cell was produced by means of a new diffusion-layer-less technology. Source-side injection programming is applicable to the new flash cell; therefore, the cell programming time is reduced to 1 /spl mu/s. The smallest memory cell (0.0162 /spl mu/m/sup 2//bit) achieved to date was accomplished by using a 90-nm technology node and applying multi-level cell technology.

A giga-scale assist-gate (AG)-AND-type flash memory cell with 20-MB/s programming throughput for content-downloading applications

Proposes a new AND-type flash memory cell with an assist gate (AG), which has achieved a 20-MB/s programming throughput. For high-speed parallel programming on the order of kilobytes, fast cell programming (10 ps) and an extremely low channel current (I/sub ds/ /spl les/ 100 nA/cell) are necessary. These features were achieved by using the low current source-side injection method in which the AG was used as a program gate. The memory cell size has also been reduced to 0.104 /spl mu/m/sup 2/ by taking advantage of an AG using field isolation and a self-aligned floating gate. These technologies are the keys to giga-scale flash memories, of which the main application is content downloading.

Constant-charge-injection programming for 10-MB/s multilevel AG-AND flash memories

The demand for high-density, high-speed programming in flash memories has been increasing because their expanding applications in portable equipment such as digital still cameras and music players. A multilevel technique is one of the most effective approaches for improving memory density. But long cell programming time and precise control of the memory cells threshold voltage (Vth) degrade its programming performance. To realize fast cell programming, we have developed a so-called assist-gate (AG)-AND-type flash cell, in which programming is performed by source side channel hot electron injection (SSI). In this paper, we developed a constant-charge-injection programming, which realizes fast precise control of Vth by suppressing the characteristic deviation. By utilizing proposed scheme, we achieved. 10.3-MB/s programming throughput in multilevel AG-AND flash memories.

Scalable 3-D vertical chain-cell-type phase-change memory with 4F2 poly-Si diodes

A three-dimensional (3-D) vertical chain-cell-type phase-change memory (VCCPCM) for next-generation large-capacity storage was developed. The VCCPCM features formation of memory holes in multi-layered stacked gates by using a single mask and a memory array without a selection transistor. As a result of this configuration, the number of process steps for fabricating the VCCPCM is reduced. The excellent scalability of the VCCPCMs new phase-change material makes it possible to reduce the cell size beyond the scaling limit of flash memory. In addition, a poly-silicon selection diode makes it possible to reduce the cell factor to 4F2. Consequently, relative cost of the VCCPCM compared to 3-D flash memory is reduced to 0.2.

10-MB/s multi-level programming of Gb-scale flash memory enabled by new AG-AND cell technology

This paper describes the first exhaustive study of a multi-level flash memory cell that achieves a programming throughput of over 10 MB/s. We reveal that increasing the individual cell programming speed (2 /spl mu/s), reducing the distribution in cell programming speeds (1.2 V), and reducing the inter-floating gate coupling to reduce Vth shift (0.15 V) are required. These three specifications are achieved by a new AG-AND cell technology consisting of self-aligned isolated punch-through stopper (SAIPTS) and U-shaped floating. This results in multilevel programming faster than 10 MB/s for the first time.

Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories

Constant-charge-injection programming (CCIP) has been proposed as a way to achieve high-speed multilevel programming in flash memories. In order to achieve high programming throughput in multilevel flash memory, programming method must provide: 1) high-speed cell-programming; 2) high programming efficiency; and 3) highly uniform programming characteristics. Conventional source-side channel-hot-electron injection (SSI) programming realizes both fast cell-programming and high programming efficiency, but the large cell-to-cell variation in programming speed with SSI is a problem. CCIP reduces the characteristic variation of SSI programming and satisfies all of the above requirements. By applying CCIP to 2-bit/cell AG-AND flash memory, the high programming throughput of 10.3 MB/s is obtained with no area penalty. This is 1.8 times faster than the throughput with conventional SSI programming.

A conformal ruthenium electrode for MIM capacitors in Gbit DRAMs using the CVD technology based on oxygen-controlled surface reaction

We have developed a novel CVD-Ru technique, clarified the growth mechanism and fabricated BST capacitors. The growth mechanism is dominated by the surface reaction which is rate-determined by the oxygen supply. Well-tuned conditions enable fabrication of any type of storage node: a concave type with a uniform 20-nm film thickness and a pillar type from a buried film. The electrode/BST interface is degraded by the reduction-oxidation reaction during the Ru-CVD, but post-annealing restores the ideal I-V characteristics.

2.8-GB/s-write and 670-MB/s-erase operations of a 3D vertical chain-cell-type phase-change-memory array

A high-programming-throughput three-dimensional (3D) vertical chain-cell-type phase-change memory (VCCPCM) array for a next-generation storage device was fabricated. To increase the number of write cells at one time by reducing resistance of bit and source lines, the VCCPCM array includes plate electrodes and double-gate vertical-chain-selection MOSs with 5-nm-thick poly-Si channels. In addition, CO2 laser annealing enhances the drivability of a poly-Si cell MOS to 680 μA/μm to suppress energy loss in the cell MOS. In addition to write throughput, erase throughput is increased by erasing memory cells in a “bundle” by channel heating (called “bundle erase”). GeSbTe CVD with high uniformity is also developed.