Hideaki Kurata
Hitachi
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Publication
Featured researches published by Hideaki Kurata.
symposium on vlsi circuits | 2006
Hideaki Kurata; Kazuo Otsuga; Akira Kotabe; Shinya Kajiyama; Taro Osabe; Yoshitaka Sasago; S. Narumi; Kenji Tokami; Shiro Kamohara; O. Tsuchiya
This paper describes for the first time the observation of the threshold voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory. We acquired large-scale data of Vth fluctuation and confirm the existence of the tail bits generated by RTS. The amount of Vth broadening due to the tail bits becomes larger as the scaling advances, and reaches to more than 0.3 V in 45-nm node. Thus the RTS becomes prominent issue for the design of multilevel flash memory in 45-nm node and beyond
international electron devices meeting | 2006
Naoki Tega; Hiroshi Miki; Taro Osabe; Akira Kotabe; Kazuo Otsuga; Hideaki Kurata; Shiro Kamohara; Kenji Tokami; Yoshihiro Ikeda; Renichi Yamada
A threshold voltage fluctuation (DeltaVth) due to random telegraph signal (RTS) in a floating-gate (FG) flash memory was investigated. From statistical analysis of the DeltaVth, we found an anomalously large DeltaVth at high percentage region of the DeltaVth distribution, which is caused by a complex RTS. Since the ratio of the complex RTS among the RTS is increased by charge injection to tunnel oxide, the dispersion of the DeltaVth distribution increases after program/erase (P/E) cycle. Since the DeltaVth due to the complex RTS is much larger than the simple RTS, the complex RTS become one of the reliability issues in larger capacity flash memory, especially after P/E cycle
IEEE Journal of Solid-state Circuits | 2007
Hideaki Kurata; Kazuo Otsuga; Akira Kotabe; Shinya Kajiyama; Taro Osabe; Yoshitaka Sasago; Shunichi Narumi; Kenji Tokami; Shiro Kamohara; Osamu Tsuchiya
Threshold-voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory was observed for the first time. A large amount of data of Vth fluctuation was acquired by using a 90-nm-node memory array, and it was confirmed that a few memory cells have large RTS fluctuation exceeding 0.2 V. It was found that program-and-erase cycles increase Vth amplitude in a flash memory. It was also found by simulation and measurement that tail-bits are generated due to RTS in multilevel flash operation. The amount of Vth broadening due to the tail-bits was estimated to become larger as the scaling of memory cells advances and reaches more than 0.3 V in the 45-nm node. These results thus demonstrate that RTS will become a prominent issue in designing multilevel flash memory in the 45-nm node and beyond.
international electron devices meeting | 2003
Yoshitaka Sasago; Hideaki Kurata; T. Arigane; Kazuo Otsuga; Takashi Kobayashi; Yoshihiro Ikeda; T. Fukumura; S. Narumi; A. Sato; T. Terauchi; Masahiro Shimizu; S. Noda; K. Kozakai; O. Tsuchiya; K. Furusawa
The first true 2-F/sup 2//bit flash cell with a programming throughput of 10 MB/s was developed. In this cell, diffusion-layer local bit lines of an assist-gate AND-type flash are replaced by inversion-layer ones under assist gates. The bit-line pitch is thus reduced to 2 F. A drain-disturbance-free and soft-write-free flash cell was produced by means of a new diffusion-layer-less technology. Source-side injection programming is applicable to the new flash cell; therefore, the cell programming time is reduced to 1 /spl mu/s. The smallest memory cell (0.0162 /spl mu/m/sup 2//bit) achieved to date was accomplished by using a 90-nm technology node and applying multi-level cell technology.
international electron devices meeting | 2001
Takashi Kobayashi; Yoshitaka Sasago; Hideaki Kurata; Shunichi Saeki; Yasushi Goto; T. Arigane; Yutaka Okuyama; Hitoshi Kume; Katsutaka Kimura
Proposes a new AND-type flash memory cell with an assist gate (AG), which has achieved a 20-MB/s programming throughput. For high-speed parallel programming on the order of kilobytes, fast cell programming (10 ps) and an extremely low channel current (I/sub ds/ /spl les/ 100 nA/cell) are necessary. These features were achieved by using the low current source-side injection method in which the AG was used as a program gate. The memory cell size has also been reduced to 0.104 /spl mu/m/sup 2/ by taking advantage of an AG using field isolation and a self-aligned floating gate. These technologies are the keys to giga-scale flash memories, of which the main application is content downloading.
symposium on vlsi circuits | 2002
Hideaki Kurata; Shunichi Saeki; Takashi Kobayashi; Yoshitaka Sasago; Takayuki Kawahara
The demand for high-density, high-speed programming in flash memories has been increasing because their expanding applications in portable equipment such as digital still cameras and music players. A multilevel technique is one of the most effective approaches for improving memory density. But long cell programming time and precise control of the memory cells threshold voltage (Vth) degrade its programming performance. To realize fast cell programming, we have developed a so-called assist-gate (AG)-AND-type flash cell, in which programming is performed by source side channel hot electron injection (SSI). In this paper, we developed a constant-charge-injection programming, which realizes fast precise control of Vth by suppressing the characteristic deviation. By utilizing proposed scheme, we achieved. 10.3-MB/s programming throughput in multilevel AG-AND flash memories.
symposium on vlsi technology | 2004
Taro Osabe; T. Ishii; Toshiyuki Mine; T. Sano; T. Arigane; T. Fukumura; Hideaki Kurata; S. Saeki; Y. Ikeda; K. Yano
We present the first experimental investigation of the lateral charge-injection length for silicon nanocrystal memory cells programmed with source-side injection (SSI). Charge-pumping measurements reveal that the injection length of SSI programming is reducible to 24 nm and suggest the possibility of scaling down the nanocrystal memory for 2-bit/cell operation to the 90-65-nm range of technology nodes.
IEEE Sensors Journal | 2013
Tatsuo Nakagawa; Akihiko Hyodo; Kenji Kogo; Hideaki Kurata; Kenichi Osada; Shigeru Oho
A novel contactless method for measuring liquid level through an opaque container is proposed. A millimeter-wave Doppler sensor is developed to “see” (i.e., sense) through a target container and measure the liquid level on the basis of the absorption of millimeter waves in liquid. One of the challenges is to accurately measure liquid level (within sub-millimeter error) despite the inherently large beam diameter of the millimeter wave due to diffraction. A piezoelectric vibrator enables accurate measurement by reflecting a limited portion of the spread beam and modulating it in frequency to distinguish it from the other portion of the beam. A prototype measurement system is fabricated and evaluated. The feasibility of our proposed method for clearly detecting an air-liquid interface concealed in an opaque container is confirmed experimentally. The nonlinearity error of the measured liquid level is within ±0.5 mm .
international reliability physics symposium | 2007
Hiroshi Miki; Taro Osabe; Naoki Tega; Akira Kotabe; Hideaki Kurata; Kenji Tokami; Y. Bceda; Shiro Kamohara; Renichi Yamada
Random telegraph signals (RTS) in fluctuations of threshold voltage are analyzed using massive readout data in scaled flash memories. A novel quantitative analytical method is proposed to evaluate parameters of the RTS, such as amplitudes and mean time spent in individual states. This evaluation gives us a statistical view of parameters of the RTS as well as their correlations. All of the parameters were found to follow log-normal distribution and to show weak mutual dependences. Possible origins of the distributions are discussed. We also studied evolution of RTS during program/erase operations of flash memories and point out its potential similarity with breakdown phenomena in gate oxide
international electron devices meeting | 2002
Yoshitaka Sasago; T. Arigane; Hideaki Kurata; Shunichi Saeki; Yasushi Goto; Shiro Kamohara; Takashi Kobayashi; Hitoshi Kume
This paper describes the first exhaustive study of a multi-level flash memory cell that achieves a programming throughput of over 10 MB/s. We reveal that increasing the individual cell programming speed (2 /spl mu/s), reducing the distribution in cell programming speeds (1.2 V), and reducing the inter-floating gate coupling to reduce Vth shift (0.15 V) are required. These three specifications are achieved by a new AG-AND cell technology consisting of self-aligned isolated punch-through stopper (SAIPTS) and U-shaped floating. This results in multilevel programming faster than 10 MB/s for the first time.