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Yoshiyuki Suehiro

Fujitsu

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Publication

Featured researches published by Yoshiyuki Suehiro.

custom integrated circuits conference | 1988

A 120 K-gate usable CMOS sea of gates packing 1.3 M transistors

Yoshiyuki Suehiro; Daisuke Miura; Mitsugu Naitoh; Sadao Tsutsumi; Takehide Shirato

A CMOS sea of gates with 160 K basic cells for random logic and memories is reported. Because of the unique architecture, the LSI offers flexible configuration of RAMs, ROMs, and PLAs (programmable logic arrays) with high density and suitable routing areas for random logic circuits, and results in the utilization of 120 K basic cells. It is fabricated with CMOS 1.0- mu m triple-metal-layer process technology.<<ETX>>

Archive | 1985

Gate array integrated circuit device and method thereof for providing various bit/word constructions

Masato Igarashi; Yoshiyuki Suehiro

Archive | 1988

Master slice type integrated circuit

Masayuki Naganuma; Yoshiyuki Suehiro

Archive | 1985

Semiconductor device incorporating memory test pattern generating circuit

Mitsugu Naitoh; Yoshiyuki Suehiro

Archive | 1985

Semiconductor memory incorporating a test pattern generator

Mitsugu Naitoh; Yoshiyuki Suehiro

Archive | 1985

GATE ARRAY INTEGRATED CIRCUIT DEVICE AND PRODUCTION METHOD THEREFOR

Masato Igarashi; Yoshiyuki Suehiro

Archive | 1988

Integrierte Schaltung vom Typ "Masterslice". Integrated circuit type "Master Slice".

Masayuki Naganuma; Yoshiyuki Suehiro

Archive | 1988

Integrierte Schaltung vom Typ "Masterslice"

Masayuki Naganuma; Yoshiyuki Suehiro

Archive | 1988

Integrated circuit type "Master Slice".

Masayuki Naganuma; Yoshiyuki Suehiro

Archive | 1985

Semiconductor memory test pattern generator.

Mitsugu Naitoh; Yoshiyuki Suehiro

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Mitsugu Naitoh

Fujitsu

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Masayuki Naganuma

Fujitsu

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Masato Igarashi

Fujitsu

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Daisuke Miura

Fujitsu

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Sadao Tsutsumi

Fujitsu

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Takehide Shirato

Fujitsu

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