You-Ru Lin

High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme

A high performance 22/20nm CMOS bulk FinFET achieves the best in-class N/P Ion values of 1200/1100 μA/μm for Ioff=100nA/μm at 1V. Excellent device electrostatic control is demonstrated for gate length (Lgate) down to 20nm. Dual-Epitaxy and multiple stressors are essential to boost the device performance. Dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly CMOS process flow. This dual-WF approach provides excellent Vth roll-off immunity in the short-channel regime that allows properly positioning the long-channel device Vth. Enhanced 193nm immersion lithography has enabled the stringent requirements of the 22/20nm ground rules. Reliability of our advanced HK/MG stack is promising. Excellent SRAM static noise margin at 0.45V is reported.

High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

Technology challenges and solutions in the development and fabrication of high-density three dimensional (3D) chip integration structures have been investigated. Critical 3D integrated circuit (IC) enabling technologies, such as through silicon via (TSV), wiring and redistribution layer (RDL), wafer thinning and handling, micro-bump (µ-bump) processes and joining, that form the building blocks for 3D IC technology were developed based on established Si foundry technologies. Test vehicles (TVs) have been designed to develop and optimize the processes, structures, as well as to evaluate the performance, yield and reliability of the 3D integration scheme.

Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking

High density through-silicon-via (TSV) and cost-effective 3D die-to-wafer integration scheme are proposed as best-in-class foundry solutions for high-end CMOS chips at 28 nm node and beyond. Key processes include: TSV formation, extreme thinning of the TSV wafer and die-to-wafer assembly. The impact of extreme thinning on device threshold voltage, leakage currents, and Ion-Ioff characteristics of bulk CMOS devices with and without e-SiGe/CESL stressors has been minimized. The presence of TSV caused no significant changes in Cu/ELK reliability. These excellent characteristics suggest the 300mm 3D-IC processes are promising and suitable for adoption in next generation integrated circuits and interconnects.

Influences of surface reconstruction on the atomic-layer-deposited HfO2/Al2O3/n-InAs metal-oxide-semiconductor capacitors

We report the characteristics of HfO2/Al2O3/n-InAs metal-oxide-semiconductor capacitors on different reconstructed surface InAs substrates. The HfO2/Al2O3 gate dielectric films deposited on InAs were used to study the interfacial reaction. Compared with (2×4)-surface sample, improvements of capacitance-voltage characteristics for (1×1)-surface sample with lower frequency-dependent capacitance dispersion and higher inversion capacitance are attributed to lower indium composition and less arsenic oxide at Al2O3/InAs interface, as confirmed by x-ray photoelectron spectroscopy. It indicates that the equivalent dangling bond of cations and anions on (1×1)-surface sample tends to avoid the oxidization process and become less pinning.

Orthotropic stress field induced by TSV and its impact on device performance

An orthotropic stress field was observed in the vicinity of the Cu-filled TSV on nominal (100) silicon substrate from both μRaman measured data and validated FEM result. The orthotropic elastic behavior of silicon in the (100) plane is believed to be the reason. The FEM model was further validated by the comparison with the measured electrical data, and used to predict the device performance shift under the influence of the TSV-induced stress. The performance shift pattern also showed an orthotropic pattern. This finding has profound implication on 3D silicon stacking design rule and system integration.

InAlP-Capped (100) Ge nFETs with 1.06 nm EOT: Achieving record high peak mobility and first integration on 300 mm Si substrate

InAlP-capped Ge nFETs with sub-400 °C process modules were reported. Ge nFETs on Ge substrates with InAlP/Al2O3/HfO2 as gate dielectrics demonstrate the highest reported Ge (100) peak μeff for inversion mode devices. In addition, the gate stack with HfO2 directly deposited on the InAlP cap was implemented in Ge nFETs on 300 mm Si substrates for the first time. This leads to the realization of long-channel Ge nFETs with 1.06 nm EOT, high drive current, excellent S, and low gate leakage current. InAlP is a good passivation technique for Ge nFET gate stack formation, and could enable the use of Ge channel for both nFETs and pFETs in future high performance and low power logic applications.

In 0.7 Ga 0.3 As channel n-MOSFETs with a novel self-aligned Ni-InGaAs contact formed using a salicide-like metallization process

Spacer-less In0.7Ga0.3As n-MOSFETs with self-aligned Ni-InGaAs contacts formed using a direct reaction between Ni and InGaAs were demonstrated. A novel salicide-like metallization process was developed to achieve self-aligned Ni-InGaAs contacts, comprising the steps of Ni reaction with InxGa1−xAs and selective removal of excess Ni. Dopantless n-MOSFETs with metallic Ni-InGaAs source/drain (S/D) and n-MOSFETs with Si-doped S/D and Ni-InGaAs contacts were compared. Si implant performed before the metallization effectively suppressed the off-state current IOFF by more than 10 times.

High performance Ge CMOS with novel InAlP-passivated channels for future sub-10 nm technology node applications

We report the first realization of high performance Ge CMOS using a novel InAlP passivation scheme. The large conduction band and valence band offsets between InAlP and Ge confine electrons and holes within the Ge channel for n-FETs and p-FETs, respectively. The InAlP cap reduces scattering due to high-K/InAlP interface traps and boosts carrier mobility. As a result, a record high electron mobility μ_EFF of ~958 cm²/V·s at N_INV of 6×10¹¹ cm^-2 was achieved for Ge(100) n-FETs, and a high peak hole mobility of ~390 cm²/V·s was obtained for Ge(100) p-FETs. High on-state currents I_ON of 39.5 μA/μm and 31.2 μA/μm were achieved at gate overdrive |V_GS-V_TH| = 1 V and |V_DS| = 1 V for the n-FETs and p-FETs, respectively, with a gate length L_G of ~3 μm. In addition, for the first time, this novel InAlP passivation technique was integrated into Ge n-FinFETs, and good control of short channel effects (SCEs) was achieved.

Improvement of defect reduction in semi-polar GaN grown on shallow-trenched Si(001) substrate

The improved design of sub-micron trenches on Si(001) substrate was demonstrated for defect suppression in semi-polar selectively-grown GaN layers. Cathodoluminescence and transmission electron microscopy measurements revealed a dramatically decreased density of threading dislocations and stacking faults near the surface of the overgrown GaN layer when the trench width ranged from 500 to 1500 nm. It was observed that defects were effectively trapped inside the trench when the ratio of trench depth to the SiO2 thickness is less than 0.66. In addition, a significant reduction of intrinsic polarization electric field was achieved for the InGaN/GaN multiple quantum well on the GaN selectively grown from the Si trenches.

Cathodoluminescence studies of GaAs nano-wires grown on shallow-trench-patterned Si

The optical properties of GaAs nano-wires grown on shallow-trench-patterned Si(001) substrates were investigated by cathodoluminescence. The results showed that when the trench width ranges from 80 to 100 nm, the emission efficiency of GaAs can be enhanced and is stronger than that of a homogeneously grown epilayer. The suppression of non-radiative centers is attributed to the trapping of both threading dislocations and planar defects at the trench sidewalls. This approach demonstrates the feasibility of growing nano-scaled GaAs-based optoelectronic devices on Si substrates.