Clement Hsingjen Wann

Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET's

The normal and reverse short-channel effect of LDD MOSFETs with lateral channel-engineering (pocket or halo implant) has been investigated. An analytical model is developed which can predict V/sub th/ as a function of L/sub eff/, V/sub DS/, V/sub BS/, and pocket parameters down to 0.1-/spl mu/m channel length. The new model shows that the V/sub th/ roll-up component due to pocket implant has an exponential dependence on channel length and is determined roughly by (N/sub p/)/sup 1/4 /L/sub p/. The validity of the model is verified by both experimental data and two-dimensional (2-D) numerical simulation. On the basis of the model, a methodology to optimize the minimum channel length L/sub min/ is presented. The theoretical optimal pocket implant performance is to achieve an L/sub min/ approximately 55/spl sim/60% that of a uniform-channel MOSFET without pocket implant, which is a significant (over one technology generation) improvement. The process design window of pocket implant is analyzed. The design tradeoff between the improvement of short-channel immunity and the other device electrical performance is also discussed.

A 25-nm gate-length FinFET transistor module for 32nm node

FinFET is the most promising double-gate transistor architecture [1] to extend scaling over planar device. We present a high-performance and low-power FinFET module at 25 nm gate length. When normalized to the actual fin perimeter, N-FinFET and P-FinFET have 1200 and 915 µA/µm drive current respectively at 100nA/µm leakage under 1V. To our knowledge this is the best FinFET drive current at such scaled gate length. This scaled gate length enables this FinFET transistor for 32nm node insertion. With aggressive fin pitch scaling, the effective transistor width is approximately 1.9X and 2.7X over planar for typical logic and SRAM on the same layout area (i.e., silicon real estate). Due to superior electrostatics and reduced random dopant fluctuation, this high drive current can be readily traded with VDD scaling for low power.

Demonstration of scaled Ge p-channel FinFETs integrated on Si

We report the first demonstration of scaled Ge p-channel FinFET devices fabricated on a Si bulk FinFET baseline using the Aspect-Ratio-Trapping (ART) technique [1]. Excellent subthreshold characteristics (long-channel subthreshold swing SS=76mV/dec at 0.5V), good SCE control and high transconductance (1.2 mS/μm at 1V, 1.05 mS/μm at 0.5V) are achieved. The Ge FinFET presented in this work exhibits highest gm/SS at Vdd=1V reported for non-planar unstrained Ge pFETs to date.

A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology

We show that FinFET, a leading transistor architecture candidate of choice for high performance CPU applications [1–3], can also be extended for general purpose SoC applications by proper device optimization. We demonstrate superior, best-in-its-class performance to our knowledge, as well as multi-Vt flexibility for low-operating power (LOP) applications. By high-k/metal-gate (HK/MG) and process flow optimizations, significant drive current (ION) improvement and leakage current (IOFF) reduction have been achieved through equivalent oxide thickness (EOT) scaling and carrier mobility improvement. N-FinFET and P-FinFET achieve, when normalized to Weff (Weff=2xHf+Wf), ION of 1325 µA/µm and 1000 µA/µm at 1 nA/µm leakage current under VDD of 1 V, and 960 uA/um and 690 uA/um at 1 nA/um under Vdd of 0.8V, respectively. This FinFET transistor module is promising for a 32/28nm SoC technology.

Influences of surface reconstruction on the atomic-layer-deposited HfO2/Al2O3/n-InAs metal-oxide-semiconductor capacitors

We report the characteristics of HfO2/Al2O3/n-InAs metal-oxide-semiconductor capacitors on different reconstructed surface InAs substrates. The HfO2/Al2O3 gate dielectric films deposited on InAs were used to study the interfacial reaction. Compared with (2×4)-surface sample, improvements of capacitance-voltage characteristics for (1×1)-surface sample with lower frequency-dependent capacitance dispersion and higher inversion capacitance are attributed to lower indium composition and less arsenic oxide at Al2O3/InAs interface, as confirmed by x-ray photoelectron spectroscopy. It indicates that the equivalent dangling bond of cations and anions on (1×1)-surface sample tends to avoid the oxidization process and become less pinning.

Self-aligned contact metallization technology for III-V metal-oxide-semiconductor field effect transistors

The demonstration of a salicidelike self-aligned contact technology for III-V metal-oxide-semiconductor field-effect transistors (MOSFETs) is reported. A thin and continuous crystalline germanium-silicon (GeSi) layer was selectively formed on n+ doped gallium arsenide (GaAs) regions by epitaxy. A new self-aligned nickel germanosilicide (NiGeSi) Ohmic contact with good morphology was achieved using a two-step annealing process with precise conversion of the GeSi layer into NiGeSi. NiGeSi contact with the contact resistivity (ρc) of 1.57 Ω mm and sheet resistance (Rsh) of 2.8 Ω/◻ was achieved. The NiGeSi-based self-aligned contact technology is promising for future integration in high performance III-V MOSFETs.

Ge Epitaxial Growth on GaAs Substrates for Application to Ge-Source/Drain GaAs MOSFETs

Ge films were epitaxially grown on GaAs(100) substrates and Ga 0.88 In 0.12 As(100) virtual substrates using an ultrahigh vacuum/ chemical vapor deposition system. The incubation time of Ge growth depends on Ga(In)As surfaces that were processed by different wet chemical solutions. Growth behaviors, such as island growth at the initial stages and selective growth into recessed regions of GaAs, were studied by transmission electron microscopy. To test the quality of Ge grown on GaAs, an n + -Ge/p-GaAs diode was fabricated. We propose that through Ge selective epitaxial growth, Ge can be used as the source-drain of a GaAs metal-oxide-semiconductor field-effect transistor (MOSFET) to overcome some intrinsic limitations of this device.

Re-examination of the extraction of MOS interface-state density by C?V stretchout and conductance methods

The extraction of interface-state density by the stretchout of MOS C?V (Terman method) is re-examined. It is shown that the typical 1?MHz frequency is not nearly high enough to get rid of the interface-state contribution to the MOS capacitance. When coupled with a bias-dependent trap time constant (?), this could result in a severe underestimate of the interface-state density. The ?conductance method?, on the other hand, can extract the interface-state density accurately if the MOS is biased in depletion and if ? ? 1/? is within the measured frequency range. Also, the robustness of the conductance method subject to errors in the estimated oxide capacitance, as well as its extendibility into regions of weak and strong inversion is investigated. Furthermore, two cases of false peaks under the conductance method are mentioned: the first due to a small tunneling leakage in thin oxides and the second due to a high density of bulk-oxide traps.

III–V MOSFETs with a new self-aligned contact

We report the first demonstration of III–V n-MOSFETs with self-aligned contact technology. The self-aligned contact was formed using a salicide-like process which is compatible with CMOS process flow. A new epitaxy process was developed to selectively form a thin continuous germanium-silicon (GeSi) layer on gallium arsenide (GaAs) source and drain (S/D) regions. Nickel was deposited and annealed to form NiGeSi, and unreacted metal was removed. A second anneal diffuses Ge and Si into GaAs to form heavily n+ doped regions, and a novel self-aligned nickel germanosilicide (NiGeSi) ohmic contact was achieved. MOSFETs with the new self-aligned metallization process were realized.

Classification and benchmarking of III–V MOSFETs for CMOS

A classification scheme for III–V MOSFETs for future CMOS is proposed and n-channel devices are benchmarked both within the group of III–V MOSFETs and in comparison with state-of-the-art silicon MOSFETs. Metrics which are based on the first derivative of drain current (Id) vs gate voltage (Vgs) are found to be most suitable for benchmarking technologies of widely diverging maturity level. Although recently reported III–V MOSFETs exhibit markedly improved performance, they still lag state-of the-art Si MOSFETs. However, Schottky gate III–V devices with an InAs channel layer already outperform silicon MOSFETs today.