Young-don Choi

A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and cost-effectiveness [1]. Besides implementations with standard interfaces like NOR flash or LPDDR2-NVM, application-oriented approaches using PRAM as main-memory or storage-class memory have been researched [2-3]. These studies suggest that noticeable merits can be achieved by using PRAM in improving power consumption, system cost, etc. However, relatively low chip density and insufficient write bandwidth of PRAMs are obstacles to better system performance. In this paper, we present an 8Gb PRAM with 40MB/s write bandwidth featuring 8Mb sub-array core architecture with 20nm diode-switched PRAM cells [4]. When an external high voltage is applied, the write bandwidth can be extended as high as 133MB/s.

A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW

In mobile systems, the demand for the energy saving continues to require a low power memory sub-system. During the last decade, the floating-gate flash memory has been an indispensable low power memory solution. However, NOR flash memory has begun to show difficulties in scaling due to the devices reliability and yield issues. Over the past few years, phase-change random access memory (PRAM) has emerged as an alternative non-volatile memory (NVM) owing to its promising scalability and low cost process [1,2]. In this paper, a PRAM, implemented in a 58nm PRAM process with a low power double-data-rate nonvolatile memory (LPDDR2-N) interface, is presented [3].

11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory

The advent of emerging technologies such as cloud computing, big data, the internet of things and mobile computing is producing a tremendous amount of data. In the era of big data, storage devices with versatile characteristics are required for ultra-fast processing, higher capacity storage, lower cost, and lower power operation. SSDs employing 3D NAND are a promising to meet these requirements. Since the introduction of 3D NAND technology to marketplace in 2014 [1], the memory array size has nearly doubled every year [2,3]. To continue scaling 3D NAND array density, it is essential to scale down vertically to minimize total mold height. However, vertical scaling results in critical problems such as increasing WL capacitance and non-uniformity of stacked WLs due to variation in the channel hole diameter. To tackle these issues, this work proposes schemes for programming speed improvement and power reduction, and on-chip processing algorithms for error correction.

A 5V-only 16M flash memory using a contactless array of source-side injection cells

The source side injection technology coupled with a modified virtual ground contactless array architecture is effective in addressing high density FLASH requirements. We describe a single supply 16 Mbit chip developed in a 0.7 /spl mu/m triple-poly double metal process using a 3.36 /spl mu/m/sup 2/ cell. The design challenge is to implement all the necessary array interface circuitry while maintaining a high array-to-chip area efficiency. This implementation requires unique decoding circuitry on the bitlines and cell control gates.

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel

A 1-Gbit DRAM with 5.8-Gb/s/pin unidirectional differential I/Os was implemented by 70 nm DRAM process and a main memory module with dual in-line memory module was assembled. The implemented DRAM chips have control methods for core noise injection and a cyclic redundancy check (CRC) generator for outer-data inner-command architecture. Measurements for bit error rate and jitter performance of the transmitter was performed on an electrical test board which emulates the real memory systems environment. Also, the effect on power noise was analyzed from the DRAM chips with three class values of power decoupling capacitance for the peripheral part. The results show that no additional coding for the differential I/O protection in DRAM, like CRC, is required up to 5.8-Gb/s/pin operation.

Channel BER Measurement for a 5.8Gb/s/pin unidirectional differential I/O for DRAM application

A 5.8 Gb/s/pin DRAM with unidirectional differential I/Os and 1 Gbit memory core was designed and 23.2 GB/s memory module was assembled. Tx BER measurement on an electrical test board similar to real memory sub-systempsilas environment was performed and the results show that no additional coding for the differential I/O protection, like CRC, seems to be required up to 5.8 Gb/s/pin operation. Also, an efficient timing usage method using matched path for a possible implementation of CRC computation in ODIC architecture was proposed.

Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM

Phase-change random access memory (PRAM) is considered to be one of the most promising storage class memory candidates. In this paper, several circuit techniques are introduced to satisfy the target yield and sensing time requirements of an 8-Gb PRAM. First, we propose a temperature-tracking reference current generator to compensate for the variation in data current caused by the change in the resistance of phase-change materials. Second, an adaptive precharge scheme to solve the problem of large parasitic resistances and capacitances of a global bitline is proposed. Finally, we introduce noise compensation schemes to reduce coupling noise. The verification of the proposed circuit techniques is performed by HSPICE simulation using the 0.25- μm model parameters used in peripheral circuit of Samsungs 20 nm PRAM technology. The sensing scheme using temperature tracking reference current generator achieves 9.32σ ( ~ 100%) of read access pass yield in 8-Gb PRAM and 99 ns of the sensing time is achieved using the adaptive precharge scheme and noise compensation schemes.

A 1.2V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package employing F-chip for low power and high performance storage applications

A 1.2 V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package incorporating 16-die stacked 512-Gb NAND flash memories and F-Chip is presented. To meet the performance requirements of storage devices for higher capacity and faster data throughput, the 2nd generation F-Chip is developed. The F-Chip presents a dual bi-directional transceiver architecture including data retiming and training techniques to adaptively improve signal integrity. Besides, the F-Chip supports 1.2 V I/O for low power storage applications. This work, as a result, shows 33% improvement of eye-opening performances and 41% reduction of I/O power consumption compared to the previous generation.