Chulbum Kim

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

A monolithic 64 Gb MLC NAND flash based on 21 nm process technology has been developed. The device consists of 4-plane arrays and provides page size of up to 32 KB. It also features a newly developed asynchronous DDR interface that can support up to the maximum bandwidth of 400 MB/s. To improve performance and reliability, on-chip randomizer, soft data readout, and incremental bit line pre-charge scheme have been developed.

7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers

Todays explosive demand for data transfer is accelerating the development of non-volatile memory with even larger capacity and cheaper cost. Since the introduction of 3D technology in 2014 [1], V-NAND is believed to be a successful alternative to planar NAND and is quickly displacing planar NAND in the SSD market, due to its performance, reliability, and cost competitiveness. V-NAND has also eliminated the cell-to-cell interference problem by forming an atomic layer for charge trapping [2], which enables further technology scaling. However, the etching technology required for creating a channel hole cannot keep up with the market-driven WL stack requirement. Therefore, total mold height reduction is unavoidable and this creates several problems. 1) reduced mold height increases resistance and capacitance for WLs due to the thinner layers being used. 2) channel hole critical dimension (CD) variation becomes problematic because the additional mold stack height aggravates uniformity, thereby producing WL resistance variation. Consequently, read and program performance degradation is inevitable, furthermore their optimization becomes more challenging.

A 159mm 2 32nm 32Gb MLC NAND-flash memory with 200MB/s asynchronous DDR interface

Providing both low cost and high storage capacity by means of device scaling and multi-level cell has been a fundamental feature in developing of NAND flash memory to meet an ever-growing flash market. Recently, however, a high speed interface like DDR (Double Data Rate) was newly adopted in NAND flash to satisfy the requirement of emerging market such as SSD (Solid-State Disk) application where high read and write throughputs are demanded [1]. In addition, as NAND scaling further, a portion of data loading and data out times in overall NAND flash performance has been increased due to increasing page size from 2K to 8K bytes, and even up to 16K bytes at two-plane operation. It significantly affects overall performance degradation in not only SSD but also conventional flash card system. The high speed interface in NAND flash, however, causes to increase chip size because of multiple memory planes more than two and additional signal buses [1]. Therefore, a high speed data interface capability with minimized chip size penalty is required in DDR NAND flash. This paper presents 159mm2 32Gb MLC NAND flash which is capable of 200MB/s read and 12MB/s write throughputs in a 32nm technology.

11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory

The advent of emerging technologies such as cloud computing, big data, the internet of things and mobile computing is producing a tremendous amount of data. In the era of big data, storage devices with versatile characteristics are required for ultra-fast processing, higher capacity storage, lower cost, and lower power operation. SSDs employing 3D NAND are a promising to meet these requirements. Since the introduction of 3D NAND technology to marketplace in 2014 [1], the memory array size has nearly doubled every year [2,3]. To continue scaling 3D NAND array density, it is essential to scale down vertically to minimize total mold height. However, vertical scaling results in critical problems such as increasing WL capacitance and non-uniformity of stacked WLs due to variation in the channel hole diameter. To tackle these issues, this work proposes schemes for programming speed improvement and power reduction, and on-chip processing algorithms for error correction.

256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers

A 48 WL stacked 256-Gb V-NAND flash memory with a 3 b MLC technology is presented. Several vertical scale-down effects such as deteriorated WL loading and variations are discussed. To enhance performance, reverse read scheme and variable-pulse scheme are presented to cope with nonuniform WL characteristics. For improved performance, dual state machine architecture is proposed to achieve optimal timing for BL and WL, respectively. Also, to maintain robust IO driver strength against PVT variations, an embedded ZQ calibration technique with temperature compensation is introduced. The chip, fabricated in a third generation of V-NAND technology, achieved a density of 2.6 Gb/mm2 with 53.2 MB/s of program throughput.

Low voltage high speed circuit designs for giga-bit DRAMs

An experimental 16 Mb DRAM for giga scale densities with a charge-amplifying boosted sensing (CABS) scheme and a new I/O large gain current sense amplifier using a cross-coupled current mirror control scheme achieves a t/sub RAC/ of 28 ns and an average operating current of 22 mA at V/sub CC/=1.5 V, t/sub RC/=70 ns, T=25/spl deg/C. This chip has been fabricated using a 0.18 /spl mu/m twin-well CMOS process with KrF lithography having transistor channel lengths of 0.32(n)/0.40(p)/spl mu/m and low resistance TiSi/sub 2/ wordlines.

An area-efficient 2 GB/s 256 Mb packet-based DRAM with daisy-chained redundancy scheme

An area-efficient packet-based 256 Mb DRAM with a 4 bank architecture and a peak bandwidth of 1.0 Gbps/pin at V/sub cc/=2.35 V, Temp=100/spl deg/C is developed. This chip features a daisy chained redundancy scheme, an area-efficient logic block placement and routing technique and a process insensitive DLL with duty error reduction scheme to overcome large chip size penalty and to improve chip yield.

A 2.5 V, 20 Gbyte/s 288 M packet-based DRAM with enhanced cell efficiency and noise immunity

Multimedia and multi-tasking computing systems demand high bandwidth and multi-bank DRAMs. To meet these requirements, several challenges regarding the chip size penalty and noise concerns associated with multi-I/O lines should be resolved. This paper describes a 2.5-V, 288-Mb DRAM with a 32-bank architecture achieving a peak bandwidth of 2.0 GB/s using both 500-MHz differential clocks and 18-I/O organization. This chip features (1) an area- and performance-efficient chip architecture with well-mixed high-speed interface circuits with DRAM peripheral circuits to increase the cell efficiency, (2) a multi-level controlled equalizing scheme and a distributed sense amplifier-driving scheme to enhance the DRAM core timing margin while digressing from the conventional sub-wordline driving scheme, having 352 cells per sub-wordline, (3) an area-efficient column redundancy scheme with multiple fuse-boxes instead of excessive spare memory cell arrays for the multi-I/O architecture, (4) a zero-DC current receiver with a counter kick-back coupling scheme to reduce the reference coupling noise, and (5) a PVT (power, voltage, time) insensitive current control scheme.

A 2.5 V, 2.0 GByte/s packet-based SDRAM with a 1.0 Gbps/pin interface

A 2.5 V, 72 Mbit packet protocol based SDRAM (PSDRAM) achieving a peak bandwidth of 2.0 GByte/s has been developed with a 0.23 /spl mu/m twin-well, 4-poly, 2-metal CMOS process. An internal Vcc of 2.0 V and V/sub term/ of 1.8 V with 0.8 V signal swing are used in the array to reduce the sensing power and I/O switching power, respectively. The total maximum chip power consumption of 1.80 W, including the average I/O switching power of 0.25 W, has been achieved when internal 16 banks are interleavingly operated with 20 ns interval commands at 2.0 GByte/s, Vcc=2.7 V, and T=25/spl deg/C.